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[xcc,pk,sim] added privileged cflush instruction
[riscv-isa-sim.git] / riscv / insns / fmov_sv.h
1 require_vector;
2 require_fp;
3 UT_LOOP_START
4 UT_LOOP_FRD = FRS1;
5 UT_LOOP_END
Simple-V augmented version of spike