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Update README
[riscv-isa-sim.git]
/
riscv
/
insns
/
jalr.h
1
reg_t tmp
=
npc
;
2
set_pc
((
RS1
+
insn
.
i_imm
()) & ~
reg_t
(
1
));
3
WRITE_RD
(
tmp
);