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Merge pull request #156 from p12nGH/noncontiguous_harts
[riscv-isa-sim.git]
/
riscv
/
insns
/
lbu.h
1
WRITE_RD
(
MMU
.
load_uint8
(
RS1
+
insn
.
i_imm
()));
projects / riscv-isa-sim.git / blob