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HEAD
[xcc,sim] eliminated vectored traps
[riscv-isa-sim.git]
/
riscv
/
insns
/
mfpcr.h
1
require_supervisor
;
2
3
reg_t val
;
4
5
switch
(
insn
.
rtype
.
rs2
)
6
{
7
case
0
:
8
val
=
sr
;
9
break
;
10
case
1
:
11
val
=
epc
;
12
break
;
13
case
2
:
14
val
=
badvaddr
;
15
break
;
16
case
3
:
17
val
=
evec
;
18
break
;
19
case
4
:
20
val
=
count
;
21
break
;
22
case
5
:
23
val
=
compare
;
24
break
;
25
case
6
:
26
val
=
cause
;
27
break
;
28
29
case
8
:
30
val
=
MEMSIZE
>>
12
;
31
break
;
32
33
case
17
:
34
fromhost
=
val
=
sim
->
get_fromhost
();
35
break
;
36
37
case
24
:
38
val
=
pcr_k0
;
39
break
;
40
case
25
:
41
val
=
pcr_k1
;
42
break
;
43
44
default
:
45
val
= -
1
;
46
}
47
48
RDR
=
gprlen
==
64
?
val
:
sext32
(
val
);