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[xcc,sim] eliminated vectored traps
[riscv-isa-sim.git]
/
riscv
/
insns
/
mtpcr.h
1
require_supervisor
;
2
3
switch
(
insn
.
rtype
.
rs2
)
4
{
5
case
0
:
6
set_sr
(
RS1
);
7
break
;
8
case
1
:
9
epc
=
RS1
;
10
break
;
11
case
3
:
12
evec
=
RS1
;
13
break
;
14
case
4
:
15
count
=
RS1
;
16
break
;
17
case
5
:
18
interrupts_pending
&= ~(
1
<<
TIMER_IRQ
);
19
compare
=
RS1
;
20
break
;
21
22
case
16
:
23
tohost
=
RS1
;
24
sim
->
set_tohost
(
RS1
);
25
break
;
26
27
case
24
:
28
pcr_k0
=
RS1
;
29
break
;
30
case
25
:
31
pcr_k1
=
RS1
;
32
break
;
33
}