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HEAD
[xcc, sim] changed instruction format so imm12 subs for rs2
[riscv-isa-sim.git]
/
riscv
/
insns
/
mul_d.h
1
require_fp
;
2
FRDR
=
f64_mul
(
FRS1
,
FRS2
);
3
set_fp_exceptions
;