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HEAD
Fix implementation of FMIN/FMAX NaN case
[riscv-isa-sim.git]
/
riscv
/
insns
/
remuw.h
1
require_extension
(
'M'
);
2
require_rv64
;
3
reg_t lhs
=
zext32
(
RS1
);
4
reg_t rhs
=
zext32
(
RS2
);
5
if
(
rhs
==
0
)
6
WRITE_RD
(
sext32
(
lhs
));
7
else
8
WRITE_RD
(
sext32
(
lhs
%
rhs
));