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HEAD
[sim] fixed divw/remw crashing simulator
[riscv-isa-sim.git]
/
riscv
/
insns
/
remw.h
1
require_xpr64
;
2
if
(
RS2
==
0
)
3
RD
=
RS1
;
4
else if
(
int32_t
(
RS1
) ==
INT32_MIN
&&
int32_t
(
RS2
) == -
1
)
5
RD
=
0
;
6
else
7
RD
=
sext32
(
int32_t
(
RS1
) %
int32_t
(
RS2
));