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Update to new privileged spec
[riscv-isa-sim.git]
/
riscv
/
insns
/
srl.h
1
if
(
xlen
==
64
)
2
WRITE_RD
(
RS1
>> (
RS2
&
0x3F
));
3
else
4
WRITE_RD
(
sext32
((
uint32_t
)
RS1
>> (
RS2
&
0x1F
)));