1 // See LICENSE for license details.
21 processor_t
*sim_t::get_core(const std::string
& i
)
24 unsigned long p
= strtoul(i
.c_str(), &ptr
, 10);
25 if (*ptr
|| p
>= num_cores())
26 throw trap_illegal_instruction();
30 static std::string
readline(int fd
)
33 bool noncanonical
= tcgetattr(fd
, &tios
) == 0 && (tios
.c_lflag
& ICANON
) == 0;
36 for (char ch
; read(fd
, &ch
, 1) == 1; )
44 if (noncanonical
&& write(fd
, "\b \b", 3) != 3)
47 else if (noncanonical
&& write(fd
, &ch
, 1) != 1)
58 void sim_t::interactive()
60 typedef void (sim_t::*interactive_func
)(const std::string
&, const std::vector
<std::string
>&);
61 std::map
<std::string
,interactive_func
> funcs
;
63 funcs
["run"] = &sim_t::interactive_run_noisy
;
64 funcs
["r"] = funcs
["run"];
65 funcs
["rs"] = &sim_t::interactive_run_silent
;
66 funcs
["reg"] = &sim_t::interactive_reg
;
67 funcs
["fregs"] = &sim_t::interactive_fregs
;
68 funcs
["fregd"] = &sim_t::interactive_fregd
;
69 funcs
["pc"] = &sim_t::interactive_pc
;
70 funcs
["mem"] = &sim_t::interactive_mem
;
71 funcs
["str"] = &sim_t::interactive_str
;
72 funcs
["until"] = &sim_t::interactive_until
;
73 funcs
["while"] = &sim_t::interactive_until
;
74 funcs
["quit"] = &sim_t::interactive_quit
;
75 funcs
["q"] = funcs
["quit"];
76 funcs
["help"] = &sim_t::interactive_help
;
77 funcs
["h"] = funcs
["help"];
81 std::cerr
<< ": " << std::flush
;
82 std::string s
= readline(2);
84 std::stringstream
ss(s
);
86 std::vector
<std::string
> args
;
90 set_procs_debug(true);
101 (this->*funcs
[cmd
])(cmd
, args
);
103 fprintf(stderr
, "Unknown command %s\n", cmd
.c_str());
107 ctrlc_pressed
= false;
110 void sim_t::interactive_help(const std::string
& cmd
, const std::vector
<std::string
>& args
)
113 "Interactive commands:\n"
114 "reg <core> [reg] # Display [reg] (all if omitted) in <core>\n"
115 "fregs <core> <reg> # Display single precision <reg> in <core>\n"
116 "fregd <core> <reg> # Display double precision <reg> in <core>\n"
117 "pc <core> # Show current PC in <core>\n"
118 "mem <hex addr> # Show contents of physical memory\n"
119 "str <hex addr> # Show NUL-terminated C string\n"
120 "until reg <core> <reg> <val> # Stop when <reg> in <core> hits <val>\n"
121 "until pc <core> <val> # Stop when PC in <core> hits <val>\n"
122 "until mem <addr> <val> # Stop when memory <addr> becomes <val>\n"
123 "while reg <core> <reg> <val> # Run while <reg> in <core> is <val>\n"
124 "while pc <core> <val> # Run while PC in <core> is <val>\n"
125 "while mem <addr> <val> # Run while memory <addr> is <val>\n"
126 "run [count] # Resume noisy execution (until CTRL+C, or [count] insns)\n"
127 "r [count] Alias for run\n"
128 "rs [count] # Resume silent execution (until CTRL+C, or [count] insns)\n"
129 "quit # End the simulation\n"
131 "help # This screen!\n"
133 "Note: Hitting enter is the same as: run 1\n"
137 void sim_t::interactive_run_noisy(const std::string
& cmd
, const std::vector
<std::string
>& args
)
139 interactive_run(cmd
,args
,true);
142 void sim_t::interactive_run_silent(const std::string
& cmd
, const std::vector
<std::string
>& args
)
144 interactive_run(cmd
,args
,false);
147 void sim_t::interactive_run(const std::string
& cmd
, const std::vector
<std::string
>& args
, bool noisy
)
149 size_t steps
= args
.size() ? atoll(args
[0].c_str()) : -1;
150 ctrlc_pressed
= false;
151 set_procs_debug(noisy
);
152 for (size_t i
= 0; i
< steps
&& !ctrlc_pressed
&& !done(); i
++)
156 void sim_t::interactive_quit(const std::string
& cmd
, const std::vector
<std::string
>& args
)
161 reg_t
sim_t::get_pc(const std::vector
<std::string
>& args
)
164 throw trap_illegal_instruction();
166 processor_t
*p
= get_core(args
[0]);
170 void sim_t::interactive_pc(const std::string
& cmd
, const std::vector
<std::string
>& args
)
172 fprintf(stderr
, "0x%016" PRIx64
"\n", get_pc(args
));
175 reg_t
sim_t::get_reg(const std::vector
<std::string
>& args
)
178 throw trap_illegal_instruction();
180 processor_t
*p
= get_core(args
[0]);
182 unsigned long r
= std::find(xpr_name
, xpr_name
+ NXPR
, args
[1]) - xpr_name
;
185 r
= strtoul(args
[1].c_str(), &ptr
, 10);
187 #define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number);
188 #include "encoding.h" // generates if's for all csrs
189 r
= NXPR
; // else case (csr name not found)
195 throw trap_illegal_instruction();
197 return p
->state
.XPR
[r
];
200 reg_t
sim_t::get_freg(const std::vector
<std::string
>& args
)
203 throw trap_illegal_instruction();
205 processor_t
*p
= get_core(args
[0]);
206 int r
= std::find(fpr_name
, fpr_name
+ NFPR
, args
[1]) - fpr_name
;
208 r
= atoi(args
[1].c_str());
210 throw trap_illegal_instruction();
212 return p
->state
.FPR
[r
];
215 void sim_t::interactive_reg(const std::string
& cmd
, const std::vector
<std::string
>& args
)
217 if (args
.size() == 1) {
218 // Show all the regs!
219 processor_t
*p
= get_core(args
[0]);
221 for (int r
= 0; r
< NXPR
; ++r
) {
222 fprintf(stderr
, "%-4s: 0x%016" PRIx64
" ", xpr_name
[r
], p
->state
.XPR
[r
]);
223 if ((r
+ 1) % 4 == 0)
224 fprintf(stderr
, "\n");
227 fprintf(stderr
, "0x%016" PRIx64
"\n", get_reg(args
));
237 void sim_t::interactive_fregs(const std::string
& cmd
, const std::vector
<std::string
>& args
)
240 f
.r
= get_freg(args
);
241 fprintf(stderr
, "%g\n",f
.s
);
244 void sim_t::interactive_fregd(const std::string
& cmd
, const std::vector
<std::string
>& args
)
247 f
.r
= get_freg(args
);
248 fprintf(stderr
, "%g\n",f
.d
);
251 reg_t
sim_t::get_mem(const std::vector
<std::string
>& args
)
253 if(args
.size() != 1 && args
.size() != 2)
254 throw trap_illegal_instruction();
256 std::string addr_str
= args
[0];
257 mmu_t
* mmu
= debug_mmu
;
260 processor_t
*p
= get_core(args
[0]);
265 reg_t addr
= strtol(addr_str
.c_str(),NULL
,16), val
;
267 addr
= strtoul(addr_str
.c_str(),NULL
,16);
272 val
= mmu
->load_uint64(addr
);
275 val
= mmu
->load_uint32(addr
);
279 val
= mmu
->load_uint16(addr
);
282 val
= mmu
->load_uint8(addr
);
288 void sim_t::interactive_mem(const std::string
& cmd
, const std::vector
<std::string
>& args
)
290 fprintf(stderr
, "0x%016" PRIx64
"\n", get_mem(args
));
293 void sim_t::interactive_str(const std::string
& cmd
, const std::vector
<std::string
>& args
)
296 throw trap_illegal_instruction();
298 reg_t addr
= strtol(args
[0].c_str(),NULL
,16);
301 while((ch
= debug_mmu
->load_uint8(addr
++)))
307 void sim_t::interactive_until(const std::string
& cmd
, const std::vector
<std::string
>& args
)
309 bool cmd_until
= cmd
== "until";
314 reg_t val
= strtol(args
[args
.size()-1].c_str(),NULL
,16);
316 val
= strtoul(args
[args
.size()-1].c_str(),NULL
,16);
318 std::vector
<std::string
> args2
;
319 args2
= std::vector
<std::string
>(args
.begin()+1,args
.end()-1);
321 auto func
= args
[0] == "reg" ? &sim_t::get_reg
:
322 args
[0] == "pc" ? &sim_t::get_pc
:
323 args
[0] == "mem" ? &sim_t::get_mem
:
329 ctrlc_pressed
= false;
335 reg_t current
= (this->*func
)(args2
);
337 if (cmd_until
== (current
== val
))
344 set_procs_debug(false);