5 #include "debug_module.h"
6 #include "debug_defines.h"
21 #define DTMCONTROL_VERSION 0xf
22 #define DTMCONTROL_ABITS (0x3f << 4)
23 #define DTMCONTROL_DBUSSTAT (3<<10)
24 #define DTMCONTROL_IDLE (7<<12)
25 #define DTMCONTROL_DBUSRESET (1<<16)
28 #define DMI_DATA (0xffffffffL<<2)
29 #define DMI_ADDRESS ((1L<<(abits+34)) - (1L<<34))
31 #define DMI_OP_STATUS_SUCCESS 0
32 #define DMI_OP_STATUS_RESERVED 1
33 #define DMI_OP_STATUS_FAILED 2
34 #define DMI_OP_STATUS_BUSY 3
38 #define DMI_OP_WRITE 2
39 #define DMI_OP_RESERVED 3
41 jtag_dtm_t::jtag_dtm_t(debug_module_t
*dm
) :
43 _tck(false), _tms(false), _tdi(false), _tdo(false),
44 dtmcontrol((abits
<< DTM_DTMCS_ABITS_OFFSET
) | 1),
45 dmi(DMI_OP_STATUS_SUCCESS
<< DTM_DMI_OP_OFFSET
),
46 _state(TEST_LOGIC_RESET
)
50 void jtag_dtm_t::reset() {
51 _state
= TEST_LOGIC_RESET
;
54 void jtag_dtm_t::set_pins(bool tck
, bool tms
, bool tdi
) {
55 const jtag_state_t next
[16][2] = {
56 /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE
, TEST_LOGIC_RESET
},
57 /* RUN_TEST_IDLE */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
58 /* SELECT_DR_SCAN */ { CAPTURE_DR
, SELECT_IR_SCAN
},
59 /* CAPTURE_DR */ { SHIFT_DR
, EXIT1_DR
},
60 /* SHIFT_DR */ { SHIFT_DR
, EXIT1_DR
},
61 /* EXIT1_DR */ { PAUSE_DR
, UPDATE_DR
},
62 /* PAUSE_DR */ { PAUSE_DR
, EXIT2_DR
},
63 /* EXIT2_DR */ { SHIFT_DR
, UPDATE_DR
},
64 /* UPDATE_DR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
65 /* SELECT_IR_SCAN */ { CAPTURE_IR
, TEST_LOGIC_RESET
},
66 /* CAPTURE_IR */ { SHIFT_IR
, EXIT1_IR
},
67 /* SHIFT_IR */ { SHIFT_IR
, EXIT1_IR
},
68 /* EXIT1_IR */ { PAUSE_IR
, UPDATE_IR
},
69 /* PAUSE_IR */ { PAUSE_IR
, EXIT2_IR
},
70 /* EXIT2_IR */ { SHIFT_IR
, UPDATE_IR
},
71 /* UPDATE_IR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
}
75 // Positive clock edge.
80 dr
|= (uint64_t) _tdi
<< (dr_length
-1);
84 ir
|= _tdi
<< (ir_length
-1);
89 _state
= next
[_state
][_tms
];
91 case TEST_LOGIC_RESET
:
109 //if (ir == IR_RESET) {
110 // Make a reset happen
118 D(fprintf(stderr
, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, "
120 _state
, _tdi
, _tdo
, _tms
, _tck
, ir
, dr
));
127 void jtag_dtm_t::capture_dr()
140 dr_length
= abits
+ 34;
143 D(fprintf(stderr
, "Unsupported IR: 0x%x\n", ir
));
146 D(fprintf(stderr
, "Capture DR; IR=0x%x, DR=0x%lx (%d bits)\n",
150 void jtag_dtm_t::update_dr()
152 D(fprintf(stderr
, "Update DR; IR=0x%x, DR=0x%lx (%d bits)\n",
157 unsigned op
= get_field(dr
, DMI_OP
);
158 uint32_t data
= get_field(dr
, DMI_DATA
);
159 unsigned address
= get_field(dr
, DMI_ADDRESS
);
164 if (op
== DMI_OP_READ
) {
166 if (dm
->dmi_read(address
, &value
)) {
167 dmi
= set_field(dmi
, DMI_DATA
, value
);
171 } else if (op
== DMI_OP_WRITE
) {
172 success
= dm
->dmi_write(address
, data
);
176 dmi
= set_field(dmi
, DMI_OP
, DMI_OP_STATUS_SUCCESS
);
178 dmi
= set_field(dmi
, DMI_OP
, DMI_OP_STATUS_FAILED
);
180 D(fprintf(stderr
, "dmi=0x%lx\n", dmi
));