1 // See LICENSE for license details.
7 mmu_t::mmu_t(sim_t
* sim
, processor_t
* proc
)
17 void mmu_t::flush_icache()
19 for (size_t i
= 0; i
< ICACHE_ENTRIES
; i
++)
23 void mmu_t::flush_tlb()
25 memset(tlb_insn_tag
, -1, sizeof(tlb_insn_tag
));
26 memset(tlb_load_tag
, -1, sizeof(tlb_load_tag
));
27 memset(tlb_store_tag
, -1, sizeof(tlb_store_tag
));
32 reg_t
mmu_t::translate(reg_t addr
, access_type type
)
37 reg_t mode
= proc
->state
.prv
;
39 if (!proc
->state
.dcsr
.cause
&& get_field(proc
->state
.mstatus
, MSTATUS_MPRV
))
40 mode
= get_field(proc
->state
.mstatus
, MSTATUS_MPP
);
42 if (get_field(proc
->state
.mstatus
, MSTATUS_VM
) == VM_MBARE
)
46 reg_t msb_mask
= (reg_t(2) << (proc
->xlen
-1))-1; // zero-extend from xlen
47 return addr
& msb_mask
;
49 return walk(addr
, type
, mode
) | (addr
& (PGSIZE
-1));
52 const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr
)
54 reg_t paddr
= translate(vaddr
, FETCH
);
56 // mmu_t::walk() returns -1 if it can't find a match. Of course -1 could also
57 // be a valid address.
58 if (paddr
== ~(reg_t
) 0 && vaddr
!= ~(reg_t
) 0) {
59 throw trap_instruction_access_fault(vaddr
);
62 if (sim
->addr_is_mem(paddr
)) {
63 refill_tlb(vaddr
, paddr
, FETCH
);
64 return (const uint16_t*)sim
->addr_to_mem(paddr
);
66 if (!sim
->mmio_load(paddr
, sizeof fetch_temp
, (uint8_t*)&fetch_temp
))
67 throw trap_instruction_access_fault(vaddr
);
72 void mmu_t::load_slow_path(reg_t addr
, reg_t len
, uint8_t* bytes
)
74 reg_t paddr
= translate(addr
, LOAD
);
75 if (sim
->addr_is_mem(paddr
)) {
76 memcpy(bytes
, sim
->addr_to_mem(paddr
), len
);
77 if (tracer
.interested_in_range(paddr
, paddr
+ PGSIZE
, LOAD
))
78 tracer
.trace(paddr
, len
, LOAD
);
80 refill_tlb(addr
, paddr
, LOAD
);
81 } else if (!sim
->mmio_load(paddr
, len
, bytes
)) {
82 throw trap_load_access_fault(addr
);
86 void mmu_t::store_slow_path(reg_t addr
, reg_t len
, const uint8_t* bytes
)
88 reg_t paddr
= translate(addr
, STORE
);
89 if (sim
->addr_is_mem(paddr
)) {
90 memcpy(sim
->addr_to_mem(paddr
), bytes
, len
);
91 if (tracer
.interested_in_range(paddr
, paddr
+ PGSIZE
, STORE
))
92 tracer
.trace(paddr
, len
, STORE
);
94 refill_tlb(addr
, paddr
, STORE
);
95 } else if (!sim
->mmio_store(paddr
, len
, bytes
)) {
96 throw trap_store_access_fault(addr
);
100 void mmu_t::refill_tlb(reg_t vaddr
, reg_t paddr
, access_type type
)
102 reg_t idx
= (vaddr
>> PGSHIFT
) % TLB_ENTRIES
;
103 reg_t expected_tag
= vaddr
>> PGSHIFT
;
105 if (tlb_load_tag
[idx
] != expected_tag
) tlb_load_tag
[idx
] = -1;
106 if (tlb_store_tag
[idx
] != expected_tag
) tlb_store_tag
[idx
] = -1;
107 if (tlb_insn_tag
[idx
] != expected_tag
) tlb_insn_tag
[idx
] = -1;
109 if (type
== FETCH
) tlb_insn_tag
[idx
] = expected_tag
;
110 else if (type
== STORE
) tlb_store_tag
[idx
] = expected_tag
;
111 else tlb_load_tag
[idx
] = expected_tag
;
113 tlb_data
[idx
] = sim
->addr_to_mem(paddr
) - vaddr
;
116 reg_t
mmu_t::walk(reg_t addr
, access_type type
, reg_t mode
)
118 int levels
, ptidxbits
, ptesize
;
119 switch (get_field(proc
->get_state()->mstatus
, MSTATUS_VM
))
121 case VM_SV32
: levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
122 case VM_SV39
: levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
123 case VM_SV48
: levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
127 bool supervisor
= mode
== PRV_S
;
128 bool pum
= get_field(proc
->state
.mstatus
, MSTATUS_PUM
);
129 bool mxr
= get_field(proc
->state
.mstatus
, MSTATUS_MXR
);
131 // verify bits xlen-1:va_bits-1 are all equal
132 int va_bits
= PGSHIFT
+ levels
* ptidxbits
;
133 reg_t mask
= (reg_t(1) << (proc
->xlen
- (va_bits
-1))) - 1;
134 reg_t masked_msbs
= (addr
>> (va_bits
-1)) & mask
;
135 if (masked_msbs
!= 0 && masked_msbs
!= mask
)
138 reg_t base
= proc
->get_state()->sptbr
<< PGSHIFT
;
139 int ptshift
= (levels
- 1) * ptidxbits
;
140 for (int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
141 reg_t idx
= (addr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
143 // check that physical address of PTE is legal
144 reg_t pte_addr
= base
+ idx
* ptesize
;
145 if (!sim
->addr_is_mem(pte_addr
))
148 void* ppte
= sim
->addr_to_mem(pte_addr
);
149 reg_t pte
= ptesize
== 4 ? *(uint32_t*)ppte
: *(uint64_t*)ppte
;
150 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
152 if (PTE_TABLE(pte
)) { // next level of page table
153 base
= ppn
<< PGSHIFT
;
154 } else if ((pte
& PTE_U
) ? supervisor
&& pum
: !supervisor
) {
156 } else if (!(pte
& PTE_V
) || (!(pte
& PTE_R
) && (pte
& PTE_W
))) {
158 } else if (type
== FETCH
? !(pte
& PTE_X
) :
159 type
== LOAD
? !(pte
& PTE_R
) && !(mxr
&& (pte
& PTE_X
)) :
160 !((pte
& PTE_R
) && (pte
& PTE_W
))) {
163 // set accessed and possibly dirty bits.
164 *(uint32_t*)ppte
|= PTE_A
| ((type
== STORE
) * PTE_D
);
165 // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
166 reg_t vpn
= addr
>> PGSHIFT
;
167 reg_t value
= (ppn
| (vpn
& ((reg_t(1) << ptshift
) - 1))) << PGSHIFT
;
175 void mmu_t::register_memtracer(memtracer_t
* t
)