1 // See LICENSE for license details.
7 mmu_t::mmu_t(char* _mem
, size_t _memsz
)
8 : mem(_mem
), memsz(_memsz
), badvaddr(0),
18 void mmu_t::flush_icache()
20 memset(icache_tag
, -1, sizeof(icache_tag
));
23 void mmu_t::flush_tlb()
25 memset(tlb_insn_tag
, -1, sizeof(tlb_insn_tag
));
26 memset(tlb_load_tag
, -1, sizeof(tlb_load_tag
));
27 memset(tlb_store_tag
, -1, sizeof(tlb_store_tag
));
32 reg_t
mmu_t::refill_tlb(reg_t addr
, reg_t bytes
, bool store
, bool fetch
)
34 reg_t idx
= (addr
>> PGSHIFT
) % TLB_ENTRIES
;
35 reg_t expected_tag
= addr
& ~(PGSIZE
-1);
37 reg_t pte
= walk(addr
);
39 reg_t pte_perm
= pte
& PTE_PERM
;
40 if (sr
& SR_S
) // shift supervisor permission bits into user perm bits
41 pte_perm
= (pte_perm
/(PTE_SX
/PTE_UX
)) & PTE_PERM
;
42 pte_perm
|= pte
& PTE_E
;
44 reg_t perm
= (fetch
? PTE_UX
: store
? PTE_UW
: PTE_UR
) | PTE_E
;
45 if(unlikely((pte_perm
& perm
) != perm
))
48 throw trap_instruction_access_fault
;
51 throw store
? trap_store_access_fault
: trap_load_access_fault
;
54 reg_t pgoff
= addr
& (PGSIZE
-1);
55 reg_t pgbase
= pte
>> PTE_PPN_SHIFT
<< PGSHIFT
;
56 reg_t paddr
= pgbase
+ pgoff
;
58 if (unlikely(tracer
.interested_in_range(pgbase
, pgbase
+ PGSIZE
, store
, fetch
)))
59 tracer
.trace(paddr
, bytes
, store
, fetch
);
62 tlb_load_tag
[idx
] = (pte_perm
& PTE_UR
) ? expected_tag
: -1;
63 tlb_store_tag
[idx
] = (pte_perm
& PTE_UW
) ? expected_tag
: -1;
64 tlb_insn_tag
[idx
] = (pte_perm
& PTE_UX
) ? expected_tag
: -1;
65 tlb_data
[idx
] = pgbase
;
71 pte_t
mmu_t::walk(reg_t addr
)
75 // the address must be a canonical sign-extended VA_BITS-bit number
76 int shift
= 8*sizeof(reg_t
) - VA_BITS
;
77 if (((sreg_t
)addr
<< shift
>> shift
) != (sreg_t
)addr
)
79 else if (!(sr
& SR_VM
))
82 pte
= PTE_E
| PTE_PERM
| ((addr
>> PGSHIFT
) << PTE_PPN_SHIFT
);
89 int ptshift
= (LEVELS
-1)*PTIDXBITS
;
90 for(reg_t i
= 0; i
< LEVELS
; i
++, ptshift
-= PTIDXBITS
)
92 reg_t idx
= (addr
>> (PGSHIFT
+ptshift
)) & ((1<<PTIDXBITS
)-1);
94 reg_t pte_addr
= base
+ idx
*sizeof(pte_t
);
98 ptd
= *(pte_t
*)(mem
+pte_addr
);
101 // if this PTE is from a larger PT, fake a leaf
102 // PTE so the TLB will work right
103 reg_t vpn
= addr
>> PGSHIFT
;
104 ptd
|= (vpn
& ((1<<(ptshift
))-1)) << PTE_PPN_SHIFT
;
106 // fault if physical addr is invalid
107 reg_t ppn
= ptd
>> PTE_PPN_SHIFT
;
108 if((ppn
<< PGSHIFT
) + (addr
& (PGSIZE
-1)) < memsz
)
112 else if(!(ptd
& PTE_T
))
115 base
= (ptd
>> PTE_PPN_SHIFT
) << PGSHIFT
;
122 void mmu_t::register_memtracer(memtracer_t
* t
)