1 // See LICENSE for license details.
11 #include "processor.h"
12 #include "memtracer.h"
15 // virtual memory configuration
17 const reg_t LEVELS
= sizeof(pte_t
) == 8 ? 3 : 2;
18 const reg_t PTIDXBITS
= 10;
19 const reg_t PGSHIFT
= PTIDXBITS
+ (sizeof(pte_t
) == 8 ? 3 : 2);
20 const reg_t PGSIZE
= 1 << PGSHIFT
;
21 const reg_t VPN_BITS
= PTIDXBITS
* LEVELS
;
22 const reg_t PPN_BITS
= 8*sizeof(reg_t
) - PGSHIFT
;
23 const reg_t VA_BITS
= VPN_BITS
+ PGSHIFT
;
34 struct icache_entry_t
{
40 // this class implements a processor's port into the virtual memory system.
41 // an MMU and instruction cache are maintained for simulator performance.
45 mmu_t(char* _mem
, size_t _memsz
);
48 // template for functions that load an aligned value from memory
49 #define load_func(type) \
50 type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
51 void* paddr = translate(addr, sizeof(type##_t), false, false); \
52 return *(type##_t*)paddr; \
55 // load value from memory at aligned address; zero extend to register width
61 // load value from memory at aligned address; sign extend to register width
67 // template for functions that store an aligned value to memory
68 #define store_func(type) \
69 void store_##type(reg_t addr, type##_t val) { \
70 void* paddr = translate(addr, sizeof(type##_t), true, false); \
71 *(type##_t*)paddr = val; \
74 // store value to memory at aligned address
80 // load instruction from memory at aligned address.
81 inline icache_entry_t
* access_icache(reg_t addr
)
83 reg_t idx
= (addr
/ sizeof(insn_t
)) % ICACHE_SIZE
;
84 icache_entry_t
* entry
= &icache
[idx
];
85 if (likely(entry
->tag
== addr
))
88 void* iaddr
= translate(addr
, sizeof(insn_t
), false, true);
90 fetch
.insn
.pad
= *(decltype(fetch
.insn
.insn
.bits())*)iaddr
;
91 fetch
.func
= proc
->decode_insn(fetch
.insn
.insn
);
93 icache
[idx
].tag
= addr
;
94 icache
[idx
].data
= fetch
;
96 reg_t paddr
= (char*)iaddr
- mem
;
97 if (!tracer
.empty() && tracer
.interested_in_range(paddr
, paddr
+ sizeof(insn_t
), false, true))
100 tracer
.trace(paddr
, sizeof(insn_t
), false, true);
105 inline insn_fetch_t
load_insn(reg_t addr
)
107 return access_icache(addr
)->data
;
110 void set_processor(processor_t
* p
) { proc
= p
; flush_tlb(); }
115 void register_memtracer(memtracer_t
*);
121 memtracer_list_t tracer
;
123 // implement an instruction cache for simulator performance
124 icache_entry_t icache
[ICACHE_SIZE
];
126 // implement a TLB for simulator performance
127 static const reg_t TLB_ENTRIES
= 256;
128 char* tlb_data
[TLB_ENTRIES
];
129 reg_t tlb_insn_tag
[TLB_ENTRIES
];
130 reg_t tlb_load_tag
[TLB_ENTRIES
];
131 reg_t tlb_store_tag
[TLB_ENTRIES
];
133 // finish translation on a TLB miss and upate the TLB
134 void* refill_tlb(reg_t addr
, reg_t bytes
, bool store
, bool fetch
);
136 // perform a page table walk for a given virtual address
137 pte_t
walk(reg_t addr
);
139 // translate a virtual address to a physical address
140 void* translate(reg_t addr
, reg_t bytes
, bool store
, bool fetch
)
141 __attribute__((always_inline
))
143 reg_t idx
= (addr
>> PGSHIFT
) % TLB_ENTRIES
;
144 reg_t expected_tag
= addr
>> PGSHIFT
;
145 reg_t
* tags
= fetch
? tlb_insn_tag
: store
? tlb_store_tag
:tlb_load_tag
;
146 reg_t tag
= tags
[idx
];
147 void* data
= tlb_data
[idx
] + addr
;
149 if (unlikely(addr
& (bytes
-1)))
150 store
? throw trap_store_address_misaligned(addr
) : throw trap_load_address_misaligned(addr
);
152 if (likely(tag
== expected_tag
))
155 return refill_tlb(addr
, bytes
, store
, fetch
);
158 friend class processor_t
;