12 // virtual memory configuration
14 const reg_t LEVELS
= sizeof(pte_t
) == sizeof(uint64_t) ? 3 : 2;
15 const reg_t PGSHIFT
= 13;
16 const reg_t PGSIZE
= 1 << PGSHIFT
;
17 const reg_t PTIDXBITS
= PGSHIFT
- (sizeof(pte_t
) == 8 ? 3 : 2);
18 const reg_t PPN_BITS
= 8*sizeof(reg_t
) - PGSHIFT
;
20 // page table entry (PTE) fields
21 #define PTE_T 0x001 // Entry is a page Table descriptor
22 #define PTE_E 0x002 // Entry is a page table Entry
23 #define PTE_R 0x004 // Referenced
24 #define PTE_D 0x008 // Dirty
25 #define PTE_UX 0x010 // User eXecute permission
26 #define PTE_UW 0x020 // User Read permission
27 #define PTE_UR 0x040 // User Write permission
28 #define PTE_SX 0x080 // Supervisor eXecute permission
29 #define PTE_SW 0x100 // Supervisor Read permission
30 #define PTE_SR 0x200 // Supervisor Write permission
31 #define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
32 #define PTE_PPN_SHIFT 13 // LSB of physical page number in the PTE
34 // this class implements a processor's port into the virtual memory system.
35 // an MMU and instruction cache are maintained for simulator performance.
39 mmu_t(char* _mem
, size_t _memsz
);
42 // template for functions that load an aligned value from memory
43 #define load_func(type) \
44 type##_t load_##type(reg_t addr) { \
45 if(unlikely(addr % sizeof(type##_t))) \
48 throw trap_load_address_misaligned; \
50 void* paddr = translate(addr, false, false); \
51 return *(type##_t*)paddr; \
54 // load value from memory at aligned address; zero extend to register width
60 // load value from memory at aligned address; sign extend to register width
66 // template for functions that store an aligned value to memory
67 #define store_func(type) \
68 void store_##type(reg_t addr, type##_t val) { \
69 if(unlikely(addr % sizeof(type##_t))) \
72 throw trap_store_address_misaligned; \
74 void* paddr = translate(addr, true, false); \
75 *(type##_t*)paddr = val; \
78 // store value to memory at aligned address
84 // load instruction from memory at aligned address.
85 // (needed because instruction alignment requirement is variable
86 // if RVC is supported)
87 // returns the instruction at the specified address, given the current
88 // RVC mode. func is set to a pointer to a function that knows how to
89 // execute the returned instruction.
90 insn_t
__attribute__((always_inline
)) load_insn(reg_t addr
, bool rvc
,
95 #ifdef RISCV_ENABLE_RVC
96 if(addr
% 4 == 2 && rvc
) // fetch across word boundary
98 void* addr_lo
= translate(addr
, false, true);
99 insn
.bits
= *(uint16_t*)addr_lo
;
101 *func
= processor_t::dispatch_table
102 [insn
.bits
% processor_t::DISPATCH_TABLE_SIZE
];
104 if(!INSN_IS_RVC(insn
.bits
))
106 void* addr_hi
= translate(addr
+2, false, true);
107 insn
.bits
|= (uint32_t)*(uint16_t*)addr_hi
<< 16;
113 reg_t idx
= (addr
/sizeof(insn_t
)) % ICACHE_ENTRIES
;
114 insn_t data
= icache_data
[idx
];
115 *func
= icache_func
[idx
];
116 if(likely(icache_tag
[idx
] == addr
))
119 // the processor guarantees alignment based upon rvc mode
120 void* paddr
= translate(addr
, false, true);
121 insn
= *(insn_t
*)paddr
;
123 icache_tag
[idx
] = addr
;
124 icache_data
[idx
] = insn
;
125 icache_func
[idx
] = *func
= processor_t::dispatch_table
126 [insn
.bits
% processor_t::DISPATCH_TABLE_SIZE
];
132 // get the virtual address that caused a fault
133 reg_t
get_badvaddr() { return badvaddr
; }
135 // get/set the page table base register
136 reg_t
get_ptbr() { return ptbr
; }
137 void set_ptbr(reg_t addr
) { ptbr
= addr
& ~(PGSIZE
-1); flush_tlb(); }
139 // keep the MMU in sync with processor mode
140 void set_supervisor(bool sup
) { supervisor
= sup
; }
141 void set_vm_enabled(bool en
) { vm_enabled
= en
; }
143 // flush the TLB and instruction cache
156 // implement a TLB for simulator performance
157 static const reg_t TLB_ENTRIES
= 256;
158 long tlb_data
[TLB_ENTRIES
];
159 reg_t tlb_insn_tag
[TLB_ENTRIES
];
160 reg_t tlb_load_tag
[TLB_ENTRIES
];
161 reg_t tlb_store_tag
[TLB_ENTRIES
];
163 // implement an instruction cache for simulator performance
164 static const reg_t ICACHE_ENTRIES
= 256;
165 insn_t icache_data
[ICACHE_ENTRIES
];
166 insn_func_t icache_func
[ICACHE_ENTRIES
];
167 reg_t icache_tag
[ICACHE_ENTRIES
];
169 // finish translation on a TLB miss and upate the TLB
170 void* refill(reg_t addr
, bool store
, bool fetch
);
172 // perform a page table walk for a given virtual address
173 pte_t
walk(reg_t addr
);
175 // translate a virtual address to a physical address
176 void* translate(reg_t addr
, bool store
, bool fetch
)
178 reg_t idx
= (addr
>> PGSHIFT
) % TLB_ENTRIES
;
180 reg_t
* tlb_tag
= fetch
? tlb_insn_tag
: store
? tlb_store_tag
:tlb_load_tag
;
181 reg_t expected_tag
= addr
& ~(PGSIZE
-1);
182 if(likely(tlb_tag
[idx
] == expected_tag
))
183 return (void*)(((long)addr
& (PGSIZE
-1)) + tlb_data
[idx
]);
185 return refill(addr
, store
, fetch
);
188 friend class processor_t
;