1 // See LICENSE for license details.
22 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
23 : sim(_sim
), mmu(_mmu
), ext(NULL
), disassembler(new disassembler_t
),
24 id(_id
), run(false), debug(false), serialized(false)
27 mmu
->set_processor(this);
29 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
35 processor_t::~processor_t()
37 #ifdef RISCV_ENABLE_HISTOGRAM
38 if (histogram_enabled
)
40 fprintf(stderr
, "PC Histogram size:%lu\n", pc_histogram
.size());
41 for(auto iterator
= pc_histogram
.begin(); iterator
!= pc_histogram
.end(); ++iterator
) {
42 fprintf(stderr
, "%0lx %lu\n", (iterator
->first
<< 2), iterator
->second
);
52 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
53 // is in supervisor mode, and in 64-bit mode, if supported, with traps
54 // and virtual memory disabled.
55 sr
= SR_S
| SR_S64
| SR_U64
;
58 // the following state is undefined upon boot-up,
59 // but we zero it for determinism
77 load_reservation
= -1;
80 void processor_t::set_debug(bool value
)
84 ext
->set_debug(value
);
87 void processor_t::set_histogram(bool value
)
89 histogram_enabled
= value
;
92 void processor_t::reset(bool value
)
98 state
.reset(); // reset the core
99 set_pcr(CSR_STATUS
, state
.sr
);
102 ext
->reset(); // reset the extension
105 struct serialize_t
{};
107 void processor_t::serialize()
112 serialized
= true, throw serialize_t();
115 void processor_t::take_interrupt()
117 int irqs
= ((state
.sr
& SR_IP
) >> SR_IP_SHIFT
) & (state
.sr
>> SR_IM_SHIFT
);
118 if (likely(!irqs
) || likely(!(state
.sr
& SR_EI
)))
121 for (int i
= 0; ; i
++)
123 throw trap_t((1ULL << ((state
.sr
& SR_S64
) ? 63 : 31)) + i
);
126 static void commit_log(state_t
* state
, reg_t pc
, insn_t insn
)
128 #ifdef RISCV_ENABLE_COMMITLOG
129 if (state
->sr
& SR_EI
) {
130 uint64_t mask
= (insn
.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn
.length() * 8))) - 1;
131 if (state
->log_reg_write
.addr
) {
132 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
") %c%2" PRIu64
" 0x%016" PRIx64
"\n",
135 state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
136 state
->log_reg_write
.addr
>> 1,
137 state
->log_reg_write
.data
);
139 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
")\n", pc
, insn
.bits() & mask
);
142 state
->log_reg_write
.addr
= 0;
146 inline void processor_t::update_histogram(size_t pc
)
148 #ifdef RISCV_ENABLE_HISTOGRAM
149 size_t idx
= pc
>> 2;
154 static reg_t
execute_insn(processor_t
* p
, reg_t pc
, insn_fetch_t fetch
)
156 reg_t npc
= fetch
.func(p
, fetch
.insn
, pc
);
157 commit_log(p
->get_state(), pc
, fetch
.insn
);
158 p
->update_histogram(pc
);
162 static void update_timer(state_t
* state
, size_t instret
)
164 uint64_t count0
= (uint64_t)(uint32_t)state
->count
;
165 state
->count
+= instret
;
166 uint64_t before
= count0
- state
->compare
;
167 if (int64_t(before
^ (before
+ instret
)) < 0)
168 state
->sr
|= (1 << (IRQ_TIMER
+ SR_IP_SHIFT
));
171 static size_t next_timer(state_t
* state
)
173 return state
->compare
- (uint32_t)state
->count
;
176 void processor_t::step(size_t n
)
182 if (unlikely(!run
|| !n
))
184 n
= std::min(n
, next_timer(&state
) | 1U);
192 while (instret
++ < n
)
194 insn_fetch_t fetch
= mmu
->load_insn(pc
);
196 pc
= execute_insn(this, pc
, fetch
);
199 else while (instret
< n
)
201 size_t idx
= _mmu
->icache_index(pc
);
202 auto ic_entry
= _mmu
->access_icache(pc
);
204 #define ICACHE_ACCESS(idx) { \
205 insn_fetch_t fetch = ic_entry->data; \
207 pc = execute_insn(this, pc, fetch); \
209 if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
210 if (unlikely(ic_entry->tag != pc)) break; \
220 pc
= take_trap(t
, pc
);
222 catch(serialize_t
& s
) {}
225 update_timer(&state
, instret
);
228 reg_t
processor_t::take_trap(trap_t
& t
, reg_t epc
)
231 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
234 // switch to supervisor, set previous supervisor bit, disable interrupts
235 set_pcr(CSR_STATUS
, (((state
.sr
& ~SR_EI
) | SR_S
) & ~SR_PS
& ~SR_PEI
) |
236 ((state
.sr
& SR_S
) ? SR_PS
: 0) |
237 ((state
.sr
& SR_EI
) ? SR_PEI
: 0));
239 yield_load_reservation();
240 state
.cause
= t
.cause();
242 t
.side_effects(&state
); // might set badvaddr etc.
246 void processor_t::deliver_ipi()
249 set_pcr(CSR_CLEAR_IPI
, 1);
252 void processor_t::disasm(insn_t insn
)
254 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
255 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
256 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
259 void processor_t::set_pcr(int which
, reg_t val
)
264 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
267 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
270 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
271 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
274 state
.sr
= (val
& ~SR_IP
) | (state
.sr
& SR_IP
);
275 #ifndef RISCV_ENABLE_64BIT
276 state
.sr
&= ~(SR_S64
| SR_U64
);
278 #ifndef RISCV_ENABLE_FPU
283 state
.sr
&= ~SR_ZERO
;
284 rv64
= (state
.sr
& SR_S
) ? (state
.sr
& SR_S64
) : (state
.sr
& SR_U64
);
291 state
.evec
= val
& ~3;
297 state
.count
= (val
<< 32) | (uint32_t)state
.count
;
301 set_interrupt(IRQ_TIMER
, false);
305 state
.ptbr
= val
& ~(PGSIZE
-1);
311 set_interrupt(IRQ_IPI
, val
& 1);
320 if (state
.tohost
== 0)
329 void processor_t::set_fromhost(reg_t val
)
331 set_interrupt(IRQ_HOST
, val
!= 0);
332 state
.fromhost
= val
;
335 reg_t
processor_t::get_pcr(int which
)
347 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
353 return state
.badvaddr
;
369 return state
.count
>> 32;
371 return state
.compare
;
393 sim
->get_htif()->tick(); // not necessary, but faster
396 sim
->get_htif()->tick(); // not necessary, but faster
397 return state
.fromhost
;
416 throw trap_illegal_instruction();
419 void processor_t::set_interrupt(int which
, bool on
)
421 uint32_t mask
= (1 << (which
+ SR_IP_SHIFT
)) & SR_IP
;
428 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
430 throw trap_illegal_instruction();
433 insn_func_t
processor_t::decode_insn(insn_t insn
)
435 size_t mask
= opcode_map
.size()-1;
436 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
438 while ((insn
.bits() & desc
->mask
) != desc
->match
)
441 return rv64
? desc
->rv64
: desc
->rv32
;
444 void processor_t::register_insn(insn_desc_t desc
)
446 assert(desc
.mask
& 1);
447 instructions
.push_back(desc
);
450 void processor_t::build_opcode_map()
453 for (auto& inst
: instructions
)
454 while ((inst
.mask
& buckets
) != buckets
)
459 decltype(insn_desc_t::match
) mask
;
460 cmp(decltype(mask
) mask
) : mask(mask
) {}
461 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
462 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
463 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
464 return lhs
.match
< rhs
.match
;
467 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
469 opcode_map
.resize(buckets
);
470 opcode_store
.resize(instructions
.size() + 1);
473 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
475 opcode_map
[b
] = &opcode_store
[j
];
476 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
477 opcode_store
[j
++] = instructions
[i
++];
480 assert(j
== opcode_store
.size()-1);
481 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
482 opcode_store
[j
].rv32
= &illegal_instruction
;
483 opcode_store
[j
].rv64
= &illegal_instruction
;
486 void processor_t::register_extension(extension_t
* x
)
488 for (auto insn
: x
->get_instructions())
491 for (auto disasm_insn
: x
->get_disasms())
492 disassembler
->add_insn(disasm_insn
);
494 throw std::logic_error("only one extension may be registered");
496 x
->set_processor(this);