1 // See LICENSE for license details.
10 #include "gdbserver.h"
23 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
,
25 : debug(false), sim(sim
), ext(NULL
), disassembler(new disassembler_t
),
26 id(id
), halt_on_reset(halt_on_reset
)
28 parse_isa_string(isa
);
30 mmu
= new mmu_t(sim
, this);
34 register_base_instructions();
37 processor_t::~processor_t()
39 #ifdef RISCV_ENABLE_HISTOGRAM
40 if (histogram_enabled
)
42 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
43 for (auto it
: pc_histogram
)
44 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
52 static void bad_isa_string(const char* isa
)
54 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
58 void processor_t::parse_isa_string(const char* str
)
60 std::string lowercase
, tmp
;
61 for (const char *r
= str
; *r
; r
++)
62 lowercase
+= std::tolower(*r
);
64 const char* p
= lowercase
.c_str();
65 const char* all_subsets
= "imafdc";
70 if (strncmp(p
, "rv32", 4) == 0)
71 max_xlen
= 32, isa
= reg_t(1) << 30, p
+= 4;
72 else if (strncmp(p
, "rv64", 4) == 0)
74 else if (strncmp(p
, "rv", 2) == 0)
79 } else if (*p
== 'g') { // treat "G" as "IMAFD"
80 tmp
= std::string("imafd") + (p
+1);
82 } else if (*p
!= 'i') {
86 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
87 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
90 isa
|= 1L << (*p
- 'a');
92 if (auto next
= strchr(all_subsets
, *p
)) {
93 all_subsets
= next
+ 1;
95 } else if (*p
== 'x') {
96 const char* ext
= p
+1, *end
= ext
;
99 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
106 if (supports_extension('D') && !supports_extension('F'))
109 // advertise support for supervisor and user modes
110 isa
|= 1L << ('s' - 'a');
111 isa
|= 1L << ('u' - 'a');
114 void state_t::reset()
116 memset(this, 0, sizeof(*this));
119 mtvec
= DEFAULT_MTVEC
;
120 load_reservation
= -1;
123 void processor_t::set_debug(bool value
)
127 ext
->set_debug(value
);
130 void processor_t::set_histogram(bool value
)
132 histogram_enabled
= value
;
133 #ifndef RISCV_ENABLE_HISTOGRAM
135 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
136 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
141 void processor_t::reset()
144 state
.dcsr
.halt
= halt_on_reset
;
145 halt_on_reset
= false;
146 set_csr(CSR_MSTATUS
, state
.mstatus
);
149 ext
->reset(); // reset the extension
152 void processor_t::raise_interrupt(reg_t which
)
154 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | which
);
157 static int ctz(reg_t val
)
161 while ((val
& 1) == 0)
166 void processor_t::take_interrupt()
168 reg_t pending_interrupts
= state
.mip
& state
.mie
;
170 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
171 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
172 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
174 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
175 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
176 enabled_interrupts
|= pending_interrupts
& state
.mideleg
& -s_enabled
;
178 if (enabled_interrupts
)
179 raise_interrupt(ctz(enabled_interrupts
));
182 static bool validate_priv(reg_t priv
)
184 return priv
== PRV_U
|| priv
== PRV_S
|| priv
== PRV_M
;
187 void processor_t::set_privilege(reg_t prv
)
189 assert(validate_priv(prv
));
194 void processor_t::enter_debug_mode(uint8_t cause
)
196 state
.dcsr
.cause
= cause
;
197 state
.dcsr
.prv
= state
.prv
;
198 set_privilege(PRV_M
);
199 state
.dpc
= state
.pc
;
200 state
.pc
= DEBUG_ROM_START
;
201 //debug = true; // TODO
204 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
207 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
210 fprintf(stderr
, "core %3d: badaddr 0x%016" PRIx64
"\n", id
,
214 if (t
.cause() == CAUSE_BREAKPOINT
&& (
215 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
216 (state
.prv
== PRV_H
&& state
.dcsr
.ebreakh
) ||
217 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
218 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
219 enter_debug_mode(DCSR_CAUSE_SWBP
);
223 if (state
.dcsr
.cause
) {
224 state
.pc
= DEBUG_ROM_EXCEPTION
;
228 // by default, trap to M-mode, unless delegated to S-mode
229 reg_t bit
= t
.cause();
230 reg_t deleg
= state
.medeleg
;
231 if (bit
& ((reg_t
)1 << (max_xlen
-1)))
232 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
233 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
234 // handle the trap in S-mode
235 state
.pc
= state
.stvec
;
236 state
.scause
= t
.cause();
239 state
.sbadaddr
= t
.get_badaddr();
241 reg_t s
= state
.mstatus
;
242 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
243 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
244 s
= set_field(s
, MSTATUS_SIE
, 0);
245 set_csr(CSR_MSTATUS
, s
);
246 set_privilege(PRV_S
);
248 state
.pc
= state
.mtvec
;
250 state
.mcause
= t
.cause();
252 state
.mbadaddr
= t
.get_badaddr();
254 reg_t s
= state
.mstatus
;
255 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
256 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
257 s
= set_field(s
, MSTATUS_MIE
, 0);
258 set_csr(CSR_MSTATUS
, s
);
259 set_privilege(PRV_M
);
262 yield_load_reservation();
265 void processor_t::disasm(insn_t insn
)
267 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
268 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
269 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
272 static bool validate_vm(int max_xlen
, reg_t vm
)
274 if (max_xlen
== 64 && (vm
== VM_SV39
|| vm
== VM_SV48
))
276 if (max_xlen
== 32 && vm
== VM_SV32
)
278 return vm
== VM_MBARE
;
281 int processor_t::paddr_bits()
283 assert(xlen
== max_xlen
);
284 return max_xlen
== 64 ? 50 : 34;
287 void processor_t::set_csr(int which
, reg_t val
)
289 val
= zext_xlen(val
);
290 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
| (1 << IRQ_COP
);
291 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
296 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
300 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
304 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
305 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
308 if ((val
^ state
.mstatus
) &
309 (MSTATUS_VM
| MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_PUM
))
312 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
313 | MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_PUM
314 | (ext
? MSTATUS_XS
: 0);
316 if (validate_vm(max_xlen
, get_field(val
, MSTATUS_VM
)))
318 if (validate_priv(get_field(val
, MSTATUS_MPP
)))
321 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
323 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
324 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
326 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
328 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
330 // spike supports the notion of xlen < max_xlen, but current priv spec
331 // doesn't provide a mechanism to run RV32 software on an RV64 machine
336 reg_t mask
= MIP_SSIP
| MIP_STIP
;
337 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
341 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
344 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
348 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
349 #include "encoding.h"
351 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
354 case CSR_MUCOUNTEREN
:
355 state
.mucounteren
= val
& 7;
357 case CSR_MSCOUNTEREN
:
358 state
.mscounteren
= val
& 7;
361 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
362 | SSTATUS_XS
| SSTATUS_PUM
;
363 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
366 return set_csr(CSR_MIP
,
367 (state
.mip
& ~state
.mideleg
) | (val
& state
.mideleg
));
369 return set_csr(CSR_MIE
,
370 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
372 // upper bits of sptbr are the ASID; we only support ASID = 0
373 state
.sptbr
= val
& (((reg_t
)1 << (paddr_bits() - PGSHIFT
)) - 1);
376 case CSR_SEPC
: state
.sepc
= val
; break;
377 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
378 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
379 case CSR_SCAUSE
: state
.scause
= val
; break;
380 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
381 case CSR_MEPC
: state
.mepc
= val
; break;
382 case CSR_MTVEC
: state
.mtvec
= val
>> 2 << 2; break;
383 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
384 case CSR_MCAUSE
: state
.mcause
= val
; break;
385 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
387 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
388 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
389 // TODO: ndreset and fullreset
390 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
391 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
392 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
393 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
394 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
400 state
.dscratch
= val
;
405 reg_t
processor_t::get_csr(int which
)
411 if (!supports_extension('F'))
416 if (!supports_extension('F'))
421 if (!supports_extension('F'))
423 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
427 if ((state
.mucounteren
>> (which
& (xlen
-1))) & 1)
428 return get_csr(which
+ (CSR_MCYCLE
- CSR_CYCLE
));
433 if ((state
.mscounteren
>> (which
& (xlen
-1))) & 1)
434 return get_csr(which
+ (CSR_MCYCLE
- CSR_SCYCLE
));
436 case CSR_MUCOUNTEREN
: return state
.mucounteren
;
437 case CSR_MSCOUNTEREN
: return state
.mscounteren
;
438 case CSR_MUCYCLE_DELTA
: return 0;
439 case CSR_MUTIME_DELTA
: return 0;
440 case CSR_MUINSTRET_DELTA
: return 0;
441 case CSR_MSCYCLE_DELTA
: return 0;
442 case CSR_MSTIME_DELTA
: return 0;
443 case CSR_MSINSTRET_DELTA
: return 0;
444 case CSR_MUCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
445 case CSR_MUTIME_DELTAH
: if (xlen
> 32) break; else return 0;
446 case CSR_MUINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
447 case CSR_MSCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
448 case CSR_MSTIME_DELTAH
: if (xlen
> 32) break; else return 0;
449 case CSR_MSINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
450 case CSR_MCYCLE
: return state
.minstret
;
451 case CSR_MINSTRET
: return state
.minstret
;
452 case CSR_MCYCLEH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
453 case CSR_MINSTRETH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
455 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
456 | SSTATUS_XS
| SSTATUS_PUM
;
457 reg_t sstatus
= state
.mstatus
& mask
;
458 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
459 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
460 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
463 case CSR_SIP
: return state
.mip
& state
.mideleg
;
464 case CSR_SIE
: return state
.mie
& state
.mideleg
;
465 case CSR_SEPC
: return state
.sepc
;
466 case CSR_SBADADDR
: return state
.sbadaddr
;
467 case CSR_STVEC
: return state
.stvec
;
470 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
472 case CSR_SPTBR
: return state
.sptbr
;
473 case CSR_SSCRATCH
: return state
.sscratch
;
474 case CSR_MSTATUS
: return state
.mstatus
;
475 case CSR_MIP
: return state
.mip
;
476 case CSR_MIE
: return state
.mie
;
477 case CSR_MEPC
: return state
.mepc
;
478 case CSR_MSCRATCH
: return state
.mscratch
;
479 case CSR_MCAUSE
: return state
.mcause
;
480 case CSR_MBADADDR
: return state
.mbadaddr
;
481 case CSR_MISA
: return isa
;
482 case CSR_MARCHID
: return 0;
483 case CSR_MIMPID
: return 0;
484 case CSR_MVENDORID
: return 0;
485 case CSR_MHARTID
: return id
;
486 case CSR_MTVEC
: return state
.mtvec
;
487 case CSR_MEDELEG
: return state
.medeleg
;
488 case CSR_MIDELEG
: return state
.mideleg
;
489 case CSR_TDRSELECT
: return 0;
493 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
494 v
= set_field(v
, DCSR_HWBPCOUNT
, 0);
495 v
= set_field(v
, DCSR_NDRESET
, 0);
496 v
= set_field(v
, DCSR_FULLRESET
, 0);
497 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
498 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
499 v
= set_field(v
, DCSR_DEBUGINT
, sim
->debug_module
.get_interrupt(id
));
500 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
501 v
= set_field(v
, DCSR_STOPTIME
, 0);
502 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
503 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
504 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
505 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
506 v
= set_field(v
, DCSR_HALT
, state
.dcsr
.halt
);
507 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
513 return state
.dscratch
;
515 throw trap_illegal_instruction();
518 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
520 throw trap_illegal_instruction();
523 insn_func_t
processor_t::decode_insn(insn_t insn
)
525 // look up opcode in hash table
526 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
527 insn_desc_t desc
= opcode_cache
[idx
];
529 if (unlikely(insn
.bits() != desc
.match
)) {
530 // fall back to linear search
531 insn_desc_t
* p
= &instructions
[0];
532 while ((insn
.bits() & p
->mask
) != p
->match
)
536 if (p
->mask
!= 0 && p
> &instructions
[0]) {
537 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
538 // move to front of opcode list to reduce miss penalty
539 while (--p
>= &instructions
[0])
541 instructions
[0] = desc
;
545 opcode_cache
[idx
] = desc
;
546 opcode_cache
[idx
].match
= insn
.bits();
549 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
552 void processor_t::register_insn(insn_desc_t desc
)
554 instructions
.push_back(desc
);
557 void processor_t::build_opcode_map()
560 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
561 if (lhs
.match
== rhs
.match
)
562 return lhs
.mask
> rhs
.mask
;
563 return lhs
.match
> rhs
.match
;
566 std::sort(instructions
.begin(), instructions
.end(), cmp());
568 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
569 opcode_cache
[i
] = {1, 0, &illegal_instruction
, &illegal_instruction
};
572 void processor_t::register_extension(extension_t
* x
)
574 for (auto insn
: x
->get_instructions())
577 for (auto disasm_insn
: x
->get_disasms())
578 disassembler
->add_insn(disasm_insn
);
580 throw std::logic_error("only one extension may be registered");
582 x
->set_processor(this);
585 void processor_t::register_base_instructions()
587 #define DECLARE_INSN(name, match, mask) \
588 insn_bits_t name##_match = (match), name##_mask = (mask);
589 #include "encoding.h"
592 #define DEFINE_INSN(name) \
593 REGISTER_INSN(this, name, name##_match, name##_mask)
594 #include "insn_list.h"
597 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
601 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
606 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
611 state
.mip
&= ~MIP_MSIP
;
613 state
.mip
|= MIP_MSIP
;