1 // See LICENSE for license details.
22 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
,
24 : debug(false), halt_request(false), sim(sim
), ext(NULL
), id(id
),
25 halt_on_reset(halt_on_reset
)
27 parse_isa_string(isa
);
28 register_base_instructions();
30 mmu
= new mmu_t(sim
, this);
31 disassembler
= new disassembler_t(max_xlen
);
36 processor_t::~processor_t()
38 #ifdef RISCV_ENABLE_HISTOGRAM
39 if (histogram_enabled
)
41 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
42 for (auto it
: pc_histogram
)
43 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
51 static void bad_isa_string(const char* isa
)
53 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
57 void processor_t::parse_isa_string(const char* str
)
59 std::string lowercase
, tmp
;
60 for (const char *r
= str
; *r
; r
++)
61 lowercase
+= std::tolower(*r
);
63 const char* p
= lowercase
.c_str();
64 const char* all_subsets
= "imafdc";
69 if (strncmp(p
, "rv32", 4) == 0)
70 max_xlen
= 32, isa
= reg_t(1) << 30, p
+= 4;
71 else if (strncmp(p
, "rv64", 4) == 0)
73 else if (strncmp(p
, "rv", 2) == 0)
78 } else if (*p
== 'g') { // treat "G" as "IMAFD"
79 tmp
= std::string("imafd") + (p
+1);
81 } else if (*p
!= 'i') {
85 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
86 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
87 isa
|= 1L << ('u' - 'a'); // advertise support for user mode
90 isa
|= 1L << (*p
- 'a');
92 if (auto next
= strchr(all_subsets
, *p
)) {
93 all_subsets
= next
+ 1;
95 } else if (*p
== 'x') {
96 const char* ext
= p
+1, *end
= ext
;
99 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
106 if (supports_extension('D') && !supports_extension('F'))
109 // advertise support for supervisor and user modes
110 isa
|= 1L << ('s' - 'a');
111 isa
|= 1L << ('u' - 'a');
116 void state_t::reset()
118 memset(this, 0, sizeof(*this));
121 load_reservation
= -1;
123 for (unsigned int i
= 0; i
< num_triggers
; i
++)
124 mcontrol
[i
].type
= 2;
127 void processor_t::set_debug(bool value
)
131 ext
->set_debug(value
);
134 void processor_t::set_histogram(bool value
)
136 histogram_enabled
= value
;
137 #ifndef RISCV_ENABLE_HISTOGRAM
139 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
140 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
145 void processor_t::reset()
148 state
.dcsr
.halt
= halt_on_reset
;
149 halt_on_reset
= false;
150 set_csr(CSR_MSTATUS
, state
.mstatus
);
153 ext
->reset(); // reset the extension
156 // Count number of contiguous 0 bits starting from the LSB.
157 static int ctz(reg_t val
)
161 while ((val
& 1) == 0)
166 void processor_t::take_interrupt(reg_t pending_interrupts
)
168 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
169 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
170 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
172 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
173 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
174 if (enabled_interrupts
== 0)
175 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
177 if (enabled_interrupts
)
178 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
181 void processor_t::set_privilege(reg_t prv
)
183 assert(prv
<= PRV_M
);
190 void processor_t::enter_debug_mode(uint8_t cause
)
192 fprintf(stderr
, "Entering debug mode because of cause %d", cause
);
193 state
.dcsr
.cause
= cause
;
194 state
.dcsr
.prv
= state
.prv
;
195 set_privilege(PRV_M
);
196 state
.dpc
= state
.pc
;
197 state
.pc
= debug_rom_entry();
200 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
203 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
206 fprintf(stderr
, "core %3d: badaddr 0x%016" PRIx64
"\n", id
,
210 if (state
.dcsr
.cause
) {
211 if (t
.cause() == CAUSE_BREAKPOINT
) {
212 state
.pc
= debug_rom_entry();
214 state
.pc
= DEBUG_ROM_TVEC
;
219 if (t
.cause() == CAUSE_BREAKPOINT
&& (
220 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
221 (state
.prv
== PRV_H
&& state
.dcsr
.ebreakh
) ||
222 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
223 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
224 enter_debug_mode(DCSR_CAUSE_SWBP
);
228 // by default, trap to M-mode, unless delegated to S-mode
229 reg_t bit
= t
.cause();
230 reg_t deleg
= state
.medeleg
;
231 bool interrupt
= (bit
& ((reg_t
)1 << (max_xlen
-1))) != 0;
233 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
234 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
235 // handle the trap in S-mode
236 state
.pc
= state
.stvec
;
237 state
.scause
= t
.cause();
240 state
.sbadaddr
= t
.get_badaddr();
242 reg_t s
= state
.mstatus
;
243 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
244 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
245 s
= set_field(s
, MSTATUS_SIE
, 0);
246 set_csr(CSR_MSTATUS
, s
);
247 set_privilege(PRV_S
);
249 reg_t vector
= (state
.mtvec
& 1) && interrupt
? 4*bit
: 0;
250 state
.pc
= (state
.mtvec
& ~(reg_t
)1) + vector
;
252 state
.mcause
= t
.cause();
254 state
.mbadaddr
= t
.get_badaddr();
256 reg_t s
= state
.mstatus
;
257 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
258 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
259 s
= set_field(s
, MSTATUS_MIE
, 0);
260 set_csr(CSR_MSTATUS
, s
);
261 set_privilege(PRV_M
);
264 yield_load_reservation();
267 void processor_t::disasm(insn_t insn
)
269 static uint64_t last_pc
= 1, last_bits
;
270 static uint64_t executions
= 1;
272 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
273 if (last_pc
!= state
.pc
|| last_bits
!= bits
) {
274 if (executions
!= 1) {
275 fprintf(stderr
, "core %3d: Executed %" PRIx64
" times\n", id
, executions
);
278 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
279 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
288 int processor_t::paddr_bits()
290 assert(xlen
== max_xlen
);
291 return max_xlen
== 64 ? 50 : 34;
294 void processor_t::set_csr(int which
, reg_t val
)
296 val
= zext_xlen(val
);
297 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
| (1 << IRQ_COP
);
298 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
303 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
307 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
311 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
312 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
315 if ((val
^ state
.mstatus
) &
316 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_SUM
| MSTATUS_MXR
))
319 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
320 | MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
321 | MSTATUS_MPP
| MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
322 | MSTATUS_TSR
| (ext
? MSTATUS_XS
: 0);
324 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
326 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
327 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
329 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
331 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
333 // spike supports the notion of xlen < max_xlen, but current priv spec
334 // doesn't provide a mechanism to run RV32 software on an RV64 machine
339 reg_t mask
= MIP_SSIP
| MIP_STIP
;
340 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
344 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
347 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
351 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
352 #include "encoding.h"
354 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
360 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
362 state
.minstret
= val
;
366 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
369 state
.scounteren
= val
;
372 state
.mcounteren
= val
;
375 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
376 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
;
377 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
380 reg_t mask
= MIP_SSIP
& state
.mideleg
;
381 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
384 return set_csr(CSR_MIE
,
385 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
389 state
.sptbr
= val
& (SPTBR32_PPN
| SPTBR32_MODE
);
390 if (max_xlen
== 64 && (get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_OFF
||
391 get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_SV39
||
392 get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_SV48
))
393 state
.sptbr
= val
& (SPTBR64_PPN
| SPTBR64_MODE
);
396 case CSR_SEPC
: state
.sepc
= val
; break;
397 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
398 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
399 case CSR_SCAUSE
: state
.scause
= val
; break;
400 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
401 case CSR_MEPC
: state
.mepc
= val
; break;
402 case CSR_MTVEC
: state
.mtvec
= val
& ~(reg_t
)2; break;
403 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
404 case CSR_MCAUSE
: state
.mcause
= val
; break;
405 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
407 if (!(val
& (1L << ('F' - 'A'))))
408 val
&= ~(1L << ('D' - 'A'));
410 // allow MAFDC bits in MISA to be modified
412 mask
|= 1L << ('M' - 'A');
413 mask
|= 1L << ('A' - 'A');
414 mask
|= 1L << ('F' - 'A');
415 mask
|= 1L << ('D' - 'A');
416 mask
|= 1L << ('C' - 'A');
419 isa
= (val
& mask
) | (isa
& ~mask
);
423 if (val
< state
.num_triggers
) {
429 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
430 if (mc
->dmode
&& !state
.dcsr
.cause
) {
433 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
434 mc
->select
= get_field(val
, MCONTROL_SELECT
);
435 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
436 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
437 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
438 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
439 mc
->m
= get_field(val
, MCONTROL_M
);
440 mc
->h
= get_field(val
, MCONTROL_H
);
441 mc
->s
= get_field(val
, MCONTROL_S
);
442 mc
->u
= get_field(val
, MCONTROL_U
);
443 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
444 mc
->store
= get_field(val
, MCONTROL_STORE
);
445 mc
->load
= get_field(val
, MCONTROL_LOAD
);
446 // Assume we're here because of csrw.
453 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
456 if (state
.tselect
< state
.num_triggers
) {
457 state
.tdata2
[state
.tselect
] = val
;
461 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
462 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
463 // TODO: ndreset and fullreset
464 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
465 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
466 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
467 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
468 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
474 state
.dscratch
= val
;
479 reg_t
processor_t::get_csr(int which
)
481 uint32_t ctr_en
= -1;
482 if (state
.prv
< PRV_M
)
483 ctr_en
&= state
.mcounteren
;
484 if (state
.prv
< PRV_S
)
485 ctr_en
&= state
.scounteren
;
486 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
489 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
491 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
494 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
496 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
498 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
505 if (!supports_extension('F'))
510 if (!supports_extension('F'))
515 if (!supports_extension('F'))
517 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
521 return state
.minstret
;
525 return state
.minstret
;
529 return state
.minstret
>> 32;
531 case CSR_SCOUNTEREN
: return state
.scounteren
;
532 case CSR_MCOUNTEREN
: return state
.mcounteren
;
534 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
535 | SSTATUS_XS
| SSTATUS_SUM
;
536 reg_t sstatus
= state
.mstatus
& mask
;
537 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
538 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
539 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
542 case CSR_SIP
: return state
.mip
& state
.mideleg
;
543 case CSR_SIE
: return state
.mie
& state
.mideleg
;
544 case CSR_SEPC
: return state
.sepc
;
545 case CSR_SBADADDR
: return state
.sbadaddr
;
546 case CSR_STVEC
: return state
.stvec
;
549 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
552 if (get_field(state
.mstatus
, MSTATUS_TVM
))
553 require_privilege(PRV_M
);
555 case CSR_SSCRATCH
: return state
.sscratch
;
556 case CSR_MSTATUS
: return state
.mstatus
;
557 case CSR_MIP
: return state
.mip
;
558 case CSR_MIE
: return state
.mie
;
559 case CSR_MEPC
: return state
.mepc
;
560 case CSR_MSCRATCH
: return state
.mscratch
;
561 case CSR_MCAUSE
: return state
.mcause
;
562 case CSR_MBADADDR
: return state
.mbadaddr
;
563 case CSR_MISA
: return isa
;
564 case CSR_MARCHID
: return 0;
565 case CSR_MIMPID
: return 0;
566 case CSR_MVENDORID
: return 0;
567 case CSR_MHARTID
: return id
;
568 case CSR_MTVEC
: return state
.mtvec
;
569 case CSR_MEDELEG
: return state
.medeleg
;
570 case CSR_MIDELEG
: return state
.mideleg
;
571 case CSR_TSELECT
: return state
.tselect
;
573 if (state
.tselect
< state
.num_triggers
) {
575 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
576 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
577 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
578 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
579 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
580 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
581 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
582 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
583 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
584 v
= set_field(v
, MCONTROL_M
, mc
->m
);
585 v
= set_field(v
, MCONTROL_H
, mc
->h
);
586 v
= set_field(v
, MCONTROL_S
, mc
->s
);
587 v
= set_field(v
, MCONTROL_U
, mc
->u
);
588 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
589 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
590 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
597 if (state
.tselect
< state
.num_triggers
) {
598 return state
.tdata2
[state
.tselect
];
603 case CSR_TDATA3
: return 0;
607 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
608 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
609 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
610 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
611 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
612 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
613 v
= set_field(v
, DCSR_STOPTIME
, 0);
614 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
615 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
616 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
622 return state
.dscratch
;
624 throw trap_illegal_instruction(0);
627 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
629 throw trap_illegal_instruction(0);
632 insn_func_t
processor_t::decode_insn(insn_t insn
)
634 // look up opcode in hash table
635 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
636 insn_desc_t desc
= opcode_cache
[idx
];
638 if (unlikely(insn
.bits() != desc
.match
)) {
639 // fall back to linear search
640 insn_desc_t
* p
= &instructions
[0];
641 while ((insn
.bits() & p
->mask
) != p
->match
)
645 if (p
->mask
!= 0 && p
> &instructions
[0]) {
646 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
647 // move to front of opcode list to reduce miss penalty
648 while (--p
>= &instructions
[0])
650 instructions
[0] = desc
;
654 opcode_cache
[idx
] = desc
;
655 opcode_cache
[idx
].match
= insn
.bits();
658 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
661 void processor_t::register_insn(insn_desc_t desc
)
663 instructions
.push_back(desc
);
666 void processor_t::build_opcode_map()
669 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
670 if (lhs
.match
== rhs
.match
)
671 return lhs
.mask
> rhs
.mask
;
672 return lhs
.match
> rhs
.match
;
675 std::sort(instructions
.begin(), instructions
.end(), cmp());
677 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
678 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
681 void processor_t::register_extension(extension_t
* x
)
683 for (auto insn
: x
->get_instructions())
686 for (auto disasm_insn
: x
->get_disasms())
687 disassembler
->add_insn(disasm_insn
);
689 throw std::logic_error("only one extension may be registered");
691 x
->set_processor(this);
694 void processor_t::register_base_instructions()
696 #define DECLARE_INSN(name, match, mask) \
697 insn_bits_t name##_match = (match), name##_mask = (mask);
698 #include "encoding.h"
701 #define DEFINE_INSN(name) \
702 REGISTER_INSN(this, name, name##_match, name##_mask)
703 #include "insn_list.h"
706 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
710 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
716 memset(bytes
, 0, len
);
717 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
726 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
732 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
741 void processor_t::trigger_updated()
744 mmu
->check_triggers_fetch
= false;
745 mmu
->check_triggers_load
= false;
746 mmu
->check_triggers_store
= false;
748 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
749 if (state
.mcontrol
[i
].execute
) {
750 mmu
->check_triggers_fetch
= true;
752 if (state
.mcontrol
[i
].load
) {
753 mmu
->check_triggers_load
= true;
755 if (state
.mcontrol
[i
].store
) {
756 mmu
->check_triggers_store
= true;