1 // See LICENSE for license details.
20 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
21 : sim(_sim
), mmu(_mmu
), ext(NULL
), disassembler(new disassembler_t
),
22 id(_id
), run(false), debug(false)
25 mmu
->set_processor(this);
27 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
33 processor_t::~processor_t()
40 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
41 // is in supervisor mode, and in 64-bit mode, if supported, with traps
42 // and virtual memory disabled.
43 sr
= SR_S
| SR_S64
| SR_U64
;
46 // the following state is undefined upon boot-up,
47 // but we zero it for determinism
65 load_reservation
= -1;
68 void processor_t::set_debug(bool value
)
72 ext
->set_debug(value
);
75 void processor_t::reset(bool value
)
81 state
.reset(); // reset the core
82 set_pcr(CSR_STATUS
, state
.sr
);
85 ext
->reset(); // reset the extension
88 void processor_t::take_interrupt()
90 uint32_t interrupts
= (state
.sr
& SR_IP
) >> SR_IP_SHIFT
;
91 interrupts
&= (state
.sr
& SR_IM
) >> SR_IM_SHIFT
;
93 if (interrupts
&& (state
.sr
& SR_EI
))
94 for (int i
= 0; ; i
++, interrupts
>>= 1)
96 throw trap_t((1ULL << ((state
.sr
& SR_S64
) ? 63 : 31)) + i
);
99 static void commit_log(state_t
* state
, insn_t insn
)
101 #ifdef RISCV_ENABLE_COMMITLOG
102 if (!(state
->sr
& SR_S
)) {
103 fprintf(stderr
, "\n0x%016" PRIx64
" (0x%08" PRIx32
") ", state
->pc
, insn
.bits());
104 if (state
->log_reg_write
.addr
)
105 fprintf(stderr
, "%c%02u 0x%016" PRIx64
, state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
106 state
->log_reg_write
.addr
>> 1, state
->log_reg_write
.data
);
107 state
->log_reg_write
.addr
= 0;
112 void processor_t::step(size_t n
)
118 auto count32
= decltype(state
.compare
)(state
.count
);
119 bool count_le_compare
= count32
<= state
.compare
;
120 n
= std::min(n
, size_t(state
.compare
- count32
) | 1);
126 if (debug
) // print out instructions as we go
128 for (size_t i
= 0; i
< n
; state
.count
++, i
++)
130 insn_fetch_t fetch
= mmu
->load_insn(state
.pc
);
131 disasm(fetch
.insn
.insn
);
132 commit_log(&state
, fetch
.insn
.insn
);
133 state
.pc
= fetch
.func(this, fetch
.insn
.insn
, state
.pc
);
138 size_t idx
= (state
.pc
/ sizeof(insn_t
)) % ICACHE_SIZE
;
139 auto ic_entry
= _mmu
->access_icache(state
.pc
), ic_entry_init
= ic_entry
;
141 #define ICACHE_ACCESS(idx) { \
142 insn_t insn = ic_entry->data.insn.insn; \
143 insn_func_t func = ic_entry->data.func; \
145 reg_t pc = func(this, insn, state.pc); \
146 commit_log(&state, insn); \
148 if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \
153 ICACHE_SWITCH
; // auto-generated into icache.h
156 size_t i
= ic_entry
- ic_entry_init
;
168 bool count_ge_compare
=
169 uint64_t(n
) + decltype(state
.compare
)(state
.count
) >= state
.compare
;
170 if (count_le_compare
&& count_ge_compare
)
171 set_interrupt(IRQ_TIMER
, true);
174 void processor_t::take_trap(trap_t
& t
)
177 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
178 id
, t
.name(), state
.pc
);
180 // switch to supervisor, set previous supervisor bit, disable interrupts
181 set_pcr(CSR_STATUS
, (((state
.sr
& ~SR_EI
) | SR_S
) & ~SR_PS
& ~SR_PEI
) |
182 ((state
.sr
& SR_S
) ? SR_PS
: 0) |
183 ((state
.sr
& SR_EI
) ? SR_PEI
: 0));
185 yield_load_reservation();
186 state
.cause
= t
.cause();
187 state
.epc
= state
.pc
;
188 state
.pc
= state
.evec
;
190 t
.side_effects(&state
); // might set badvaddr etc.
193 void processor_t::deliver_ipi()
196 set_pcr(CSR_CLEAR_IPI
, 1);
199 void processor_t::disasm(insn_t insn
)
201 // the disassembler is stateless, so we share it
202 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx32
") %s\n",
203 id
, state
.pc
, insn
.bits(), disassembler
->disassemble(insn
).c_str());
206 reg_t
processor_t::set_pcr(int which
, reg_t val
)
208 reg_t old_pcr
= get_pcr(which
);
213 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
216 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
219 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
220 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
223 state
.sr
= (val
& ~SR_IP
) | (state
.sr
& SR_IP
);
224 #ifndef RISCV_ENABLE_64BIT
225 state
.sr
&= ~(SR_S64
| SR_U64
);
227 #ifndef RISCV_ENABLE_FPU
232 state
.sr
&= ~SR_ZERO
;
233 rv64
= (state
.sr
& SR_S
) ? (state
.sr
& SR_S64
) : (state
.sr
& SR_U64
);
240 state
.evec
= val
& ~3;
246 state
.count
= (val
<< 32) | (uint32_t)state
.count
;
249 set_interrupt(IRQ_TIMER
, false);
253 state
.ptbr
= val
& ~(PGSIZE
-1);
259 set_interrupt(IRQ_IPI
, val
& 1);
268 if (state
.tohost
== 0)
279 void processor_t::set_fromhost(reg_t val
)
281 set_interrupt(IRQ_HOST
, val
!= 0);
282 state
.fromhost
= val
;
285 reg_t
processor_t::get_pcr(int which
)
294 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
300 return state
.badvaddr
;
314 return state
.count
>> 32;
316 return state
.compare
;
338 sim
->get_htif()->tick(); // not necessary, but faster
341 sim
->get_htif()->tick(); // not necessary, but faster
342 return state
.fromhost
;
344 throw trap_illegal_instruction();
347 void processor_t::set_interrupt(int which
, bool on
)
349 uint32_t mask
= (1 << (which
+ SR_IP_SHIFT
)) & SR_IP
;
356 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
358 throw trap_illegal_instruction();
361 insn_func_t
processor_t::decode_insn(insn_t insn
)
363 size_t mask
= opcode_map
.size()-1;
364 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
366 while ((insn
.bits() & desc
->mask
) != desc
->match
)
369 return rv64
? desc
->rv64
: desc
->rv32
;
372 void processor_t::register_insn(insn_desc_t desc
)
374 assert(desc
.mask
& 1);
375 instructions
.push_back(desc
);
378 void processor_t::build_opcode_map()
381 for (auto& inst
: instructions
)
382 while ((inst
.mask
& buckets
) != buckets
)
387 decltype(insn_desc_t::match
) mask
;
388 cmp(decltype(mask
) mask
) : mask(mask
) {}
389 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
390 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
391 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
392 return lhs
.match
< rhs
.match
;
395 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
397 opcode_map
.resize(buckets
);
398 opcode_store
.resize(instructions
.size() + 1);
401 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
403 opcode_map
[b
] = &opcode_store
[j
];
404 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
405 opcode_store
[j
++] = instructions
[i
++];
408 assert(j
== opcode_store
.size()-1);
409 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
410 opcode_store
[j
].rv32
= &illegal_instruction
;
411 opcode_store
[j
].rv64
= &illegal_instruction
;
414 void processor_t::register_extension(extension_t
* x
)
416 for (auto insn
: x
->get_instructions())
419 for (auto disasm_insn
: x
->get_disasms())
420 disassembler
->add_insn(disasm_insn
);
422 throw std::logic_error("only one extension may be registered");
424 x
->set_processor(this);