riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
  23   : sim(sim), ext(NULL), disassembler(new disassembler_t),
  24     id(id), run(false), debug(false)
  25 {
  26   parse_isa_string(isa);
  27
  28   mmu = new mmu_t(sim->mem, sim->memsz);
  29   mmu->set_processor(this);
  30
  31   reset(true);
  32
  33   register_base_instructions();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
  42     for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
  43       fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
  44     }
  45   }
  46 #endif
  47
  48   delete mmu;
  49   delete disassembler;
  50 }
  51
  52 static void bad_isa_string(const char* isa)
  53 {
  54   fprintf(stderr, "error: bad --isa option %s\n", isa);
  55   abort();
  56 }
  57
  58 void processor_t::parse_isa_string(const char* isa)
  59 {
  60   const char* p = isa;
  61   const char* all_subsets = "IMAFDC";
  62
  63   max_xlen = 64;
  64   cpuid = reg_t(2) << 62;
  65
  66   if (strncmp(p, "RV32", 4) == 0)
  67     max_xlen = 32, cpuid = 0, p += 4;
  68   else if (strncmp(p, "RV64", 4) == 0)
  69     p += 4;
  70   else if (strncmp(p, "RV", 2) == 0)
  71     p += 2;
  72
  73   cpuid |= 1L << ('S' - 'A'); // advertise support for supervisor mode
  74
  75   if (!*p)
  76     p = all_subsets;
  77   else if (*p != 'I')
  78     bad_isa_string(isa);
  79
  80   while (*p) {
  81     cpuid |= 1L << (*p - 'A');
  82
  83     if (auto next = strchr(all_subsets, *p)) {
  84       all_subsets = next + 1;
  85       p++;
  86     } else if (*p == 'X') {
  87       const char* ext = p+1, *end = ext;
  88       while (islower(*end))
  89         end++;
  90       register_extension(find_extension(std::string(ext, end - ext).c_str())());
  91       p = end;
  92     } else {
  93       bad_isa_string(isa);
  94     }
  95   }
  96
  97   if (supports_extension('D') && !supports_extension('F'))
  98     bad_isa_string(isa);
  99 }
 100
 101 void state_t::reset()
 102 {
 103   memset(this, 0, sizeof(*this));
 104   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
 105   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
 106   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
 107   pc = DEFAULT_MTVEC + 0x100;
 108   load_reservation = -1;
 109 }
 110
 111 void processor_t::set_debug(bool value)
 112 {
 113   debug = value;
 114   if (ext)
 115     ext->set_debug(value);
 116 }
 117
 118 void processor_t::set_histogram(bool value)
 119 {
 120   histogram_enabled = value;
 121 #ifndef RISCV_ENABLE_HISTOGRAM
 122   if (value) {
 123     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 124     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 125   }
 126 #endif
 127 }
 128
 129 void processor_t::reset(bool value)
 130 {
 131   if (run == !value)
 132     return;
 133   run = !value;
 134
 135   state.reset();
 136   set_csr(CSR_MSTATUS, state.mstatus);
 137
 138   if (ext)
 139     ext->reset(); // reset the extension
 140 }
 141
 142 void processor_t::raise_interrupt(reg_t which)
 143 {
 144   throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
 145 }
 146
 147 void processor_t::take_interrupt()
 148 {
 149   int priv = get_field(state.mstatus, MSTATUS_PRV);
 150   int ie = get_field(state.mstatus, MSTATUS_IE);
 151   reg_t interrupts = state.mie & state.mip;
 152
 153   if (priv < PRV_M || (priv == PRV_M && ie)) {
 154     if (interrupts & MIP_MSIP)
 155       raise_interrupt(IRQ_SOFT);
 156
 157     if (interrupts & MIP_MTIP)
 158       raise_interrupt(IRQ_TIMER);
 159
 160     if (state.fromhost != 0)
 161       raise_interrupt(IRQ_HOST);
 162   }
 163
 164   if (priv < PRV_S || (priv == PRV_S && ie)) {
 165     if (interrupts & MIP_SSIP)
 166       raise_interrupt(IRQ_SOFT);
 167
 168     if (interrupts & MIP_STIP)
 169       raise_interrupt(IRQ_TIMER);
 170   }
 171 }
 172
 173 void processor_t::check_timer()
 174 {
 175   if (sim->rtc >= state.mtimecmp)
 176     state.mip |= MIP_MTIP;
 177 }
 178
 179 void processor_t::push_privilege_stack()
 180 {
 181   reg_t s = state.mstatus;
 182   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 183   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 184   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 185   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 186   s = set_field(s, MSTATUS_PRV, PRV_M);
 187   s = set_field(s, MSTATUS_MPRV, 0);
 188   s = set_field(s, MSTATUS_IE, 0);
 189   set_csr(CSR_MSTATUS, s);
 190 }
 191
 192 void processor_t::pop_privilege_stack()
 193 {
 194   reg_t s = state.mstatus;
 195   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 196   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 197   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 198   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 199   s = set_field(s, MSTATUS_PRV2, PRV_U);
 200   s = set_field(s, MSTATUS_IE2, 1);
 201   set_csr(CSR_MSTATUS, s);
 202 }
 203
 204 void processor_t::take_trap(trap_t& t, reg_t epc)
 205 {
 206   if (debug)
 207     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 208             id, t.name(), epc);
 209
 210   state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 211   push_privilege_stack();
 212   yield_load_reservation();
 213   state.mcause = t.cause();
 214   state.mepc = epc;
 215   t.side_effects(&state); // might set badvaddr etc.
 216 }
 217
 218 void processor_t::deliver_ipi()
 219 {
 220   state.mip |= MIP_MSIP;
 221 }
 222
 223 void processor_t::disasm(insn_t insn)
 224 {
 225   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 226   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 227           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 228 }
 229
 230 static bool validate_priv(reg_t priv)
 231 {
 232   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 233 }
 234
 235 static bool validate_vm(int max_xlen, reg_t vm)
 236 {
 237   if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
 238     return true;
 239   if (max_xlen == 32 && vm == VM_SV32)
 240     return true;
 241   return vm == VM_MBARE;
 242 }
 243
 244 void processor_t::set_csr(int which, reg_t val)
 245 {
 246   switch (which)
 247   {
 248     case CSR_FFLAGS:
 249       dirty_fp_state;
 250       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 251       break;
 252     case CSR_FRM:
 253       dirty_fp_state;
 254       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 255       break;
 256     case CSR_FCSR:
 257       dirty_fp_state;
 258       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 259       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 260       break;
 261     case CSR_MTIME:
 262     case CSR_STIMEW:
 263       // this implementation ignores writes to MTIME
 264       break;
 265     case CSR_MTIMEH:
 266     case CSR_STIMEHW:
 267       // this implementation ignores writes to MTIME
 268       break;
 269     case CSR_TIMEW:
 270       val -= sim->rtc;
 271       if (xlen == 32)
 272         state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
 273       else
 274         state.sutime_delta = val;
 275       break;
 276     case CSR_TIMEHW:
 277       val = ((val << 32) - sim->rtc) >> 32;
 278       state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
 279       break;
 280     case CSR_CYCLEW:
 281     case CSR_INSTRETW:
 282       val -= state.minstret;
 283       if (xlen == 32)
 284         state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
 285       else
 286         state.suinstret_delta = val;
 287       break;
 288     case CSR_CYCLEHW:
 289     case CSR_INSTRETHW:
 290       val = ((val << 32) - state.minstret) >> 32;
 291       state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
 292       break;
 293     case CSR_MSTATUS: {
 294       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
 295         mmu->flush_tlb();
 296
 297       reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
 298                    | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
 299
 300       if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
 301         mask |= MSTATUS_VM;
 302       if (validate_priv(get_field(val, MSTATUS_PRV)))
 303         mask |= MSTATUS_PRV;
 304       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 305         mask |= MSTATUS_PRV1;
 306       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 307         mask |= MSTATUS_PRV2;
 308
 309       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 310
 311       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 312       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 313       if (max_xlen == 32)
 314         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 315       else
 316         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 317
 318       // spike supports the notion of xlen < max_xlen, but current priv spec
 319       // doesn't provide a mechanism to run RV32 software on an RV64 machine
 320       xlen = max_xlen;
 321       break;
 322     }
 323     case CSR_MIP: {
 324       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
 325       state.mip = (state.mip & ~mask) | (val & mask);
 326       break;
 327     }
 328     case CSR_MIE: {
 329       reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP;
 330       state.mie = (state.mie & ~mask) | (val & mask);
 331       break;
 332     }
 333     case CSR_SSTATUS: {
 334       reg_t ms = state.mstatus;
 335       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 336       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 337       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 338       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 339       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 340       ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
 341       return set_csr(CSR_MSTATUS, ms);
 342     }
 343     case CSR_SIP: {
 344       reg_t mask = MIP_SSIP;
 345       state.mip = (state.mip & ~mask) | (val & mask);
 346       break;
 347     }
 348     case CSR_SIE: {
 349       reg_t mask = MIP_SSIP | MIP_STIP;
 350       state.mie = (state.mie & ~mask) | (val & mask);
 351       break;
 352     }
 353     case CSR_SEPC: state.sepc = val; break;
 354     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 355     case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
 356     case CSR_SSCRATCH: state.sscratch = val; break;
 357     case CSR_MEPC: state.mepc = val; break;
 358     case CSR_MSCRATCH: state.mscratch = val; break;
 359     case CSR_MCAUSE: state.mcause = val; break;
 360     case CSR_MBADADDR: state.mbadaddr = val; break;
 361     case CSR_MTIMECMP:
 362       state.mip &= ~MIP_MTIP;
 363       state.mtimecmp = val;
 364       break;
 365     case CSR_SEND_IPI: sim->send_ipi(val); break;
 366     case CSR_MTOHOST:
 367       if (state.tohost == 0)
 368         state.tohost = val;
 369       break;
 370     case CSR_MFROMHOST: state.fromhost = val; break;
 371   }
 372 }
 373
 374 reg_t processor_t::get_csr(int which)
 375 {
 376   switch (which)
 377   {
 378     case CSR_FFLAGS:
 379       require_fp;
 380       if (!supports_extension('F'))
 381         break;
 382       return state.fflags;
 383     case CSR_FRM:
 384       require_fp;
 385       if (!supports_extension('F'))
 386         break;
 387       return state.frm;
 388     case CSR_FCSR:
 389       require_fp;
 390       if (!supports_extension('F'))
 391         break;
 392       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 393     case CSR_MTIME:
 394     case CSR_STIME:
 395     case CSR_STIMEW:
 396       return sim->rtc;
 397     case CSR_MTIMEH:
 398     case CSR_STIMEH:
 399     case CSR_STIMEHW:
 400       return sim->rtc >> 32;
 401     case CSR_TIME:
 402     case CSR_TIMEW:
 403       return sim->rtc + state.sutime_delta;
 404     case CSR_CYCLE:
 405     case CSR_CYCLEW:
 406     case CSR_INSTRET:
 407     case CSR_INSTRETW:
 408       return state.minstret + state.suinstret_delta;
 409     case CSR_TIMEH:
 410     case CSR_TIMEHW:
 411       if (xlen == 64)
 412         break;
 413       return (sim->rtc + state.sutime_delta) >> 32;
 414     case CSR_CYCLEH:
 415     case CSR_INSTRETH:
 416     case CSR_CYCLEHW:
 417     case CSR_INSTRETHW:
 418       if (xlen == 64)
 419         break;
 420       return (state.minstret + state.suinstret_delta) >> 32;
 421     case CSR_SSTATUS: {
 422       reg_t ss = 0;
 423       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 424       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 425       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 426       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 427       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 428       ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
 429       if (get_field(state.mstatus, MSTATUS64_SD))
 430         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 431       return ss;
 432     }
 433     case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
 434     case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
 435     case CSR_SEPC: return state.sepc;
 436     case CSR_SBADADDR: return state.sbadaddr;
 437     case CSR_STVEC: return state.stvec;
 438     case CSR_SCAUSE:
 439       if (max_xlen > xlen)
 440         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 441       return state.scause;
 442     case CSR_SPTBR: return state.sptbr;
 443     case CSR_SASID: return 0;
 444     case CSR_SSCRATCH: return state.sscratch;
 445     case CSR_MSTATUS: return state.mstatus;
 446     case CSR_MIP: return state.mip;
 447     case CSR_MIE: return state.mie;
 448     case CSR_MEPC: return state.mepc;
 449     case CSR_MSCRATCH: return state.mscratch;
 450     case CSR_MCAUSE: return state.mcause;
 451     case CSR_MBADADDR: return state.mbadaddr;
 452     case CSR_MTIMECMP: return state.mtimecmp;
 453     case CSR_MCPUID: return cpuid;
 454     case CSR_MIMPID: return IMPL_ROCKET;
 455     case CSR_MHARTID: return id;
 456     case CSR_MTVEC: return DEFAULT_MTVEC;
 457     case CSR_MTDELEG: return 0;
 458     case CSR_MTOHOST:
 459       sim->get_htif()->tick(); // not necessary, but faster
 460       return state.tohost;
 461     case CSR_MFROMHOST:
 462       sim->get_htif()->tick(); // not necessary, but faster
 463       return state.fromhost;
 464     case CSR_SEND_IPI: return 0;
 465     case CSR_UARCH0:
 466     case CSR_UARCH1:
 467     case CSR_UARCH2:
 468     case CSR_UARCH3:
 469     case CSR_UARCH4:
 470     case CSR_UARCH5:
 471     case CSR_UARCH6:
 472     case CSR_UARCH7:
 473     case CSR_UARCH8:
 474     case CSR_UARCH9:
 475     case CSR_UARCH10:
 476     case CSR_UARCH11:
 477     case CSR_UARCH12:
 478     case CSR_UARCH13:
 479     case CSR_UARCH14:
 480     case CSR_UARCH15:
 481       return 0;
 482   }
 483   throw trap_illegal_instruction();
 484 }
 485
 486 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 487 {
 488   throw trap_illegal_instruction();
 489 }
 490
 491 insn_func_t processor_t::decode_insn(insn_t insn)
 492 {
 493   // look up opcode in hash table
 494   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 495   insn_desc_t desc = opcode_cache[idx];
 496
 497   if (unlikely(insn.bits() != desc.match)) {
 498     // fall back to linear search
 499     insn_desc_t* p = &instructions[0];
 500     while ((insn.bits() & p->mask) != p->match)
 501       p++;
 502     desc = *p;
 503
 504     if (p->mask != 0 && p > &instructions[0]) {
 505       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 506         // move to front of opcode list to reduce miss penalty
 507         while (--p >= &instructions[0])
 508           *(p+1) = *p;
 509         instructions[0] = desc;
 510       }
 511     }
 512
 513     opcode_cache[idx] = desc;
 514     opcode_cache[idx].match = insn.bits();
 515   }
 516
 517   return xlen == 64 ? desc.rv64 : desc.rv32;
 518 }
 519
 520 void processor_t::register_insn(insn_desc_t desc)
 521 {
 522   instructions.push_back(desc);
 523 }
 524
 525 void processor_t::build_opcode_map()
 526 {
 527   struct cmp {
 528     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 529       if (lhs.match == rhs.match)
 530         return lhs.mask > rhs.mask;
 531       return lhs.match > rhs.match;
 532     }
 533   };
 534   std::sort(instructions.begin(), instructions.end(), cmp());
 535
 536   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 537     opcode_cache[i] = {1, 0, &illegal_instruction, &illegal_instruction};
 538 }
 539
 540 void processor_t::register_extension(extension_t* x)
 541 {
 542   for (auto insn : x->get_instructions())
 543     register_insn(insn);
 544   build_opcode_map();
 545   for (auto disasm_insn : x->get_disasms())
 546     disassembler->add_insn(disasm_insn);
 547   if (ext != NULL)
 548     throw std::logic_error("only one extension may be registered");
 549   ext = x;
 550   x->set_processor(this);
 551 }
 552
 553 void processor_t::register_base_instructions()
 554 {
 555   std::map<std::string, std::pair<insn_bits_t, insn_bits_t>> opcodes;
 556
 557   #define DECLARE_INSN(name, match, mask) \
 558     opcodes[#name] = std::make_pair(match, mask);
 559   #include "encoding.h"
 560   #undef DECLARE_INSN
 561
 562   #define DEFINE_INSN(name) \
 563     if (!opcodes.count(#name)) \
 564       throw std::logic_error("opcode for " #name " not found"); \
 565     REGISTER_INSN(this, name, opcodes[#name].first, opcodes[#name].second)
 566   #include "insn_list.h"
 567   #undef DEFINE_INSN
 568
 569   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 570   build_opcode_map();
 571 }