riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "common.h"
   5 #include "config.h"
   6 #include "sim.h"
   7 #include "disasm.h"
   8 #include <cinttypes>
   9 #include <cmath>
  10 #include <cstdlib>
  11 #include <iostream>
  12 #include <assert.h>
  13 #include <limits.h>
  14
  15 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  16   : sim(*_sim), mmu(*_mmu), id(_id), opcode_bits(0)
  17 {
  18   reset(true);
  19   mmu.set_processor(this);
  20
  21   #define DECLARE_INSN(name, match, mask) \
  22     register_insn(match, mask, (insn_func_t)&processor_t::rv32_##name, (insn_func_t)&processor_t::rv64_##name);
  23   #include "opcodes.h"
  24   #undef DECLARE_INSN
  25 }
  26
  27 processor_t::~processor_t()
  28 {
  29 }
  30
  31 void processor_t::reset(bool value)
  32 {
  33   if (run == !value)
  34     return;
  35   run = !value;
  36
  37   // the ISA guarantees on boot that the PC is 0x2000 and the the processor
  38   // is in supervisor mode, and in 64-bit mode, if supported, with traps
  39   // and virtual memory disabled.
  40   sr = 0;
  41   set_pcr(PCR_SR, SR_S | SR_S64 | SR_IM);
  42   pc = 0x2000;
  43
  44   // the following state is undefined upon boot-up,
  45   // but we zero it for determinism
  46   XPR.reset();
  47   FPR.reset();
  48
  49   evec = 0;
  50   epc = 0;
  51   badvaddr = 0;
  52   cause = 0;
  53   pcr_k0 = 0;
  54   pcr_k1 = 0;
  55   count = 0;
  56   compare = 0;
  57   cycle = 0;
  58   set_fsr(0);
  59 }
  60
  61 void processor_t::set_fsr(uint32_t val)
  62 {
  63   fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
  64 }
  65
  66 void processor_t::take_interrupt()
  67 {
  68   uint32_t interrupts = (sr & SR_IP) >> SR_IP_SHIFT;
  69   interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
  70
  71   if(interrupts && (sr & SR_EI))
  72     for(int i = 0; ; i++, interrupts >>= 1)
  73       if(interrupts & 1)
  74         throw interrupt_t(i);
  75 }
  76
  77 void processor_t::step(size_t n, bool noisy)
  78 {
  79   if(!run)
  80     return;
  81
  82   size_t i = 0;
  83   try
  84   {
  85     take_interrupt();
  86
  87     mmu_t& _mmu = mmu;
  88     reg_t npc = pc;
  89
  90     // execute_insn fetches and executes one instruction
  91     #define execute_insn(noisy) \
  92       do { \
  93         mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc); \
  94         if(noisy) disasm(fetch.insn, npc); \
  95         npc = fetch.func(this, fetch.insn, npc); \
  96         pc = npc; \
  97       } while(0)
  98
  99     if(noisy) for( ; i < n; i++) // print out instructions as we go
 100       execute_insn(true);
 101     else
 102     {
 103       // unrolled for speed
 104       for( ; n > 3 && i < n-3; i+=4)
 105       {
 106         execute_insn(false);
 107         execute_insn(false);
 108         execute_insn(false);
 109         execute_insn(false);
 110       }
 111       for( ; i < n; i++)
 112         execute_insn(false);
 113     }
 114   }
 115   catch(trap_t t)
 116   {
 117     // an exception occurred in the target processor
 118     take_trap(t,noisy);
 119   }
 120   catch(interrupt_t t)
 121   {
 122     take_trap((1ULL << ((sr & SR_S64) ? 63 : 31)) + t.i, noisy);
 123   }
 124
 125   cycle += i;
 126
 127   // update timer and possibly register a timer interrupt
 128   uint32_t old_count = count;
 129   count += i;
 130   if(old_count < compare && uint64_t(old_count) + i >= compare)
 131     set_interrupt(IRQ_TIMER, true);
 132 }
 133
 134 void processor_t::take_trap(reg_t t, bool noisy)
 135 {
 136   if(noisy)
 137   {
 138     if ((sreg_t)t < 0)
 139       fprintf(stderr, "core %3d: interrupt %d, epc 0x%016" PRIx64 "\n",
 140               id, uint8_t(t), pc);
 141     else
 142       fprintf(stderr, "core %3d: trap %s, epc 0x%016" PRIx64 "\n",
 143               id, trap_name(trap_t(t)), pc);
 144   }
 145
 146   // switch to supervisor, set previous supervisor bit, disable traps
 147   set_pcr(PCR_SR, (((sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
 148                   ((sr & SR_S) ? SR_PS : 0) |
 149                   ((sr & SR_EI) ? SR_PEI : 0));
 150   cause = t;
 151   epc = pc;
 152   pc = evec;
 153   badvaddr = mmu.get_badvaddr();
 154 }
 155
 156 void processor_t::deliver_ipi()
 157 {
 158   if (run)
 159     set_pcr(PCR_CLR_IPI, 1);
 160 }
 161
 162 void processor_t::disasm(insn_t insn, reg_t pc)
 163 {
 164   // the disassembler is stateless, so we share it
 165   static disassembler disasm;
 166   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
 167           id, pc, insn.bits, disasm.disassemble(insn).c_str());
 168 }
 169
 170 void processor_t::set_pcr(int which, reg_t val)
 171 {
 172   switch (which)
 173   {
 174     case PCR_SR:
 175       sr = (val & ~SR_IP) | (sr & SR_IP);
 176 #ifndef RISCV_ENABLE_64BIT
 177       sr &= ~(SR_S64 | SR_U64);
 178 #endif
 179 #ifndef RISCV_ENABLE_FPU
 180       sr &= ~SR_EF;
 181 #endif
 182 #ifndef RISCV_ENABLE_VEC
 183       sr &= ~SR_EV;
 184 #endif
 185       sr &= ~SR_ZERO;
 186       mmu.flush_tlb();
 187       break;
 188     case PCR_EPC:
 189       epc = val;
 190       break;
 191     case PCR_EVEC:
 192       evec = val;
 193       break;
 194     case PCR_COUNT:
 195       count = val;
 196       break;
 197     case PCR_COMPARE:
 198       set_interrupt(IRQ_TIMER, false);
 199       compare = val;
 200       break;
 201     case PCR_PTBR:
 202       mmu.set_ptbr(val);
 203       break;
 204     case PCR_SEND_IPI:
 205       sim.send_ipi(val);
 206       break;
 207     case PCR_CLR_IPI:
 208       set_interrupt(IRQ_IPI, val & 1);
 209       break;
 210     case PCR_K0:
 211       pcr_k0 = val;
 212       break;
 213     case PCR_K1:
 214       pcr_k1 = val;
 215       break;
 216     case PCR_TOHOST:
 217       if (tohost == 0)
 218         tohost = val;
 219       break;
 220     case PCR_FROMHOST:
 221       set_interrupt(IRQ_HOST, val != 0);
 222       fromhost = val;
 223       break;
 224   }
 225 }
 226
 227 reg_t processor_t::get_pcr(int which)
 228 {
 229   switch (which)
 230   {
 231     case PCR_SR:
 232       return sr;
 233     case PCR_EPC:
 234       return epc;
 235     case PCR_BADVADDR:
 236       return badvaddr;
 237     case PCR_EVEC:
 238       return evec;
 239     case PCR_COUNT:
 240       return count;
 241     case PCR_COMPARE:
 242       return compare;
 243     case PCR_CAUSE:
 244       return cause;
 245     case PCR_PTBR:
 246       return mmu.get_ptbr();
 247     case PCR_ASID:
 248       return 0;
 249     case PCR_FATC:
 250       mmu.flush_tlb();
 251     case PCR_HARTID:
 252       return id;
 253     case PCR_IMPL:
 254       return 1;
 255     case PCR_K0:
 256       return pcr_k0;
 257     case PCR_K1:
 258       return pcr_k1;
 259     case PCR_TOHOST:
 260       return tohost;
 261     case PCR_FROMHOST:
 262       return fromhost;
 263   }
 264   return -1;
 265 }
 266
 267 void processor_t::set_interrupt(int which, bool on)
 268 {
 269   uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
 270   if (on)
 271     sr |= mask;
 272   else
 273     sr &= ~mask;
 274 }
 275
 276 insn_func_t processor_t::decode_insn(insn_t insn)
 277 {
 278   bool rv64 = (sr & SR_S) ? (sr & SR_S64) : (sr & SR_U64);
 279
 280   auto key = insn.bits & ((1L << opcode_bits)-1);
 281   auto it = opcode_map.find(key);
 282   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
 283     if ((insn.bits & it->second.mask) == it->second.match)
 284       return rv64 ? it->second.rv64 : it->second.rv32;
 285
 286   return &processor_t::illegal_instruction;
 287 }
 288
 289 reg_t processor_t::illegal_instruction(insn_t insn, reg_t pc)
 290 {
 291   throw trap_illegal_instruction;
 292 }
 293
 294 void processor_t::register_insn(uint32_t match, uint32_t mask, insn_func_t rv32, insn_func_t rv64)
 295 {
 296   assert(mask & 1);
 297   if (opcode_bits == 0 || (mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
 298   {
 299     unsigned x = 0;
 300     while ((mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
 301            (opcode_bits == 0 || x <= opcode_bits))
 302       x++;
 303     opcode_bits = x;
 304
 305     decltype(opcode_map) new_map;
 306     for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
 307       new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
 308     opcode_map = new_map;
 309   }
 310
 311   opcode_map.insert(std::make_pair(match & ((1L<<opcode_bits)-1),
 312     (opcode_map_entry_t){match, mask, rv32, rv64}));
 313 }