12 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
13 : sim(*_sim
), mmu(*_mmu
), id(_id
), utidx(0)
17 // create microthreads
18 for (int i
=0; i
<MAX_UTS
; i
++)
19 uts
[i
] = new processor_t(&sim
, &mmu
, id
, i
);
22 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
,
24 : sim(*_sim
), mmu(*_mmu
), id(_id
), utidx(_utidx
)
27 set_sr(sr
| SR_EF
| SR_EV
);
29 // microthreads don't possess their own microthreads
30 for (int i
=0; i
<MAX_UTS
; i
++)
34 processor_t::~processor_t()
38 void processor_t::reset()
42 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
43 // is in supervisor mode, and in 64-bit mode, if supported, with traps
44 // and virtual memory disabled. we accomplish this by setting EVEC to
45 // 0x2000 and *enabling* traps, then sending the core an IPI.
46 set_sr(SR_S
| SR_SX
| SR_ET
| SR_IM
);
49 // the following state is undefined upon boot-up,
50 // but we zero it for determinism
51 memset(XPR
,0,sizeof(XPR
));
52 memset(FPR
,0,sizeof(FPR
));
76 void processor_t::set_sr(uint32_t val
)
78 sr
= val
& ~SR_ZERO
; // clear SR bits that read as zero
80 #ifndef RISCV_ENABLE_64BIT
81 sr
&= ~(SR_SX
| SR_UX
); // SX=UX=0 for RV32 implementations
83 #ifndef RISCV_ENABLE_FPU
86 #ifndef RISCV_ENABLE_RVC
89 #ifndef RISCV_ENABLE_VEC
93 // update MMU state and flush TLB
94 mmu
.set_vm_enabled(sr
& SR_VM
);
95 mmu
.set_supervisor(sr
& SR_S
);
98 // set the fixed-point register length
99 xprlen
= ((sr
& SR_S
) ? (sr
& SR_SX
) : (sr
& SR_UX
)) ? 64 : 32;
102 void processor_t::set_fsr(uint32_t val
)
104 fsr
= val
& ~FSR_ZERO
; // clear FSR bits that read as zero
107 void processor_t::vcfg()
109 if (nxpr_use
+ nfpr_use
< 2)
110 vlmax
= nxfpr_bank
* vecbanks_count
;
112 vlmax
= (nxfpr_bank
/ (nxpr_use
+ nfpr_use
- 1)) * vecbanks_count
;
114 vlmax
= std::min(vlmax
, MAX_UTS
);
117 void processor_t::setvl(int vlapp
)
119 vl
= std::min(vlmax
, vlapp
);
122 void processor_t::take_interrupt()
124 uint32_t interrupts
= interrupts_pending
;
125 interrupts
&= (sr
& SR_IM
) >> SR_IM_SHIFT
;
127 if(interrupts
&& (sr
& SR_ET
))
128 for(int i
= 0; ; i
++, interrupts
>>= 1)
130 throw (trap_t
)(trap_irq0
+ i
);
133 void processor_t::step(size_t n
, bool noisy
)
148 // execute_insn fetches and executes one instruction
149 #define execute_insn(noisy) \
151 insn = _mmu.load_insn(npc, sr & SR_EC, &func); \
152 if(noisy) disasm(insn,pc); \
153 npc = func(this, insn, npc); \
157 if(noisy
) for( ; i
< n
; i
++) // print out instructions as we go
161 // unrolled for speed
162 for( ; n
> 3 && i
< n
-3; i
+=4)
177 // an exception occurred in the target processor
181 catch(vt_command_t cmd
)
183 // this microthread has finished
185 assert(cmd
== vt_command_stop
);
197 // update timer and possibly register a timer interrupt
198 uint32_t old_count
= count
;
200 if(old_count
< compare
&& uint64_t(old_count
) + i
>= compare
)
201 interrupts_pending
|= 1 << TIMER_IRQ
;
204 void processor_t::take_trap(trap_t t
, bool noisy
)
207 printf("core %3d: trap %s, pc 0x%016llx\n",
208 id
, trap_name(t
), (unsigned long long)pc
);
210 // switch to supervisor, set previous supervisor bit, disable traps
211 set_sr((((sr
& ~SR_ET
) | SR_S
) & ~SR_PS
) | ((sr
& SR_S
) ? SR_PS
: 0));
215 badvaddr
= mmu
.get_badvaddr();
218 void processor_t::deliver_ipi()
220 interrupts_pending
|= 1 << IPI_IRQ
;
224 void processor_t::disasm(insn_t insn
, reg_t pc
)
226 printf("core %3d: 0x%016llx (0x%08x) ",id
,(unsigned long long)pc
,insn
.bits
);
228 #ifdef RISCV_HAVE_LIBOPCODES
229 disassemble_info info
;
230 INIT_DISASSEMBLE_INFO(info
, stdout
, fprintf
);
231 info
.flavour
= bfd_target_unknown_flavour
;
232 info
.arch
= bfd_arch_mips
;
233 info
.mach
= 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
234 info
.endian
= BFD_ENDIAN_LITTLE
;
235 info
.buffer
= (bfd_byte
*)&insn
;
236 info
.buffer_length
= sizeof(insn
);
237 info
.buffer_vma
= pc
;
239 int ret
= print_insn_little_mips(pc
, &info
);
240 assert(ret
== insn_length(insn
.bits
));