1 // See LICENSE for license details.
22 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
23 : sim(_sim
), mmu(_mmu
), ext(NULL
), disassembler(new disassembler_t
),
24 id(_id
), run(false), debug(false), serialized(false)
27 mmu
->set_processor(this);
29 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
35 processor_t::~processor_t()
37 #ifdef RISCV_ENABLE_HISTOGRAM
38 if (histogram_enabled
)
40 fprintf(stderr
, "PC Histogram size:%lu\n", pc_histogram
.size());
41 for(auto iterator
= pc_histogram
.begin(); iterator
!= pc_histogram
.end(); ++iterator
) {
42 fprintf(stderr
, "%0lx %lu\n", (iterator
->first
<< 2), iterator
->second
);
52 memset(this, 0, sizeof(*this));
53 mstatus
= set_field(mstatus
, MSTATUS_PRV
, PRV_M
);
54 mstatus
= set_field(mstatus
, MSTATUS_PRV1
, PRV_S
);
55 mstatus
= set_field(mstatus
, MSTATUS_PRV2
, PRV_S
);
56 #ifdef RISCV_ENABLE_64BIT
57 mstatus
= set_field(mstatus
, MSTATUS64_UA
, UA_RV64
);
58 mstatus
= set_field(mstatus
, MSTATUS64_SA
, UA_RV64
);
61 load_reservation
= -1;
64 void processor_t::set_debug(bool value
)
68 ext
->set_debug(value
);
71 void processor_t::set_histogram(bool value
)
73 histogram_enabled
= value
;
76 void processor_t::reset(bool value
)
82 state
.reset(); // reset the core
83 set_csr(CSR_MSTATUS
, state
.mstatus
);
86 ext
->reset(); // reset the extension
89 struct serialize_t
{};
91 void processor_t::serialize()
96 serialized
= true, throw serialize_t();
99 void processor_t::raise_interrupt(reg_t which
)
101 throw trap_t(((reg_t
)1 << 63) | which
);
104 void processor_t::take_interrupt()
106 int priv
= get_field(state
.mstatus
, MSTATUS_PRV
);
107 int ie
= get_field(state
.mstatus
, MSTATUS_IE
);
109 if (priv
< PRV_M
|| (priv
== PRV_M
&& ie
)) {
110 if (get_field(state
.mstatus
, MSTATUS_MSIP
))
111 raise_interrupt(IRQ_IPI
);
113 if (state
.fromhost
!= 0)
114 raise_interrupt(IRQ_HOST
);
117 if (priv
< PRV_S
|| (priv
== PRV_S
&& ie
)) {
118 if (get_field(state
.mstatus
, MSTATUS_SSIP
))
119 raise_interrupt(IRQ_IPI
);
121 if (state
.stip
&& get_field(state
.mstatus
, MSTATUS_STIE
))
122 raise_interrupt(IRQ_TIMER
);
126 static void commit_log(state_t
* state
, reg_t pc
, insn_t insn
)
128 #ifdef RISCV_ENABLE_COMMITLOG
129 if (get_field(state
->mstatus
, MSTATUS_IE
)) {
130 uint64_t mask
= (insn
.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn
.length() * 8))) - 1;
131 if (state
->log_reg_write
.addr
) {
132 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
") %c%2" PRIu64
" 0x%016" PRIx64
"\n",
135 state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
136 state
->log_reg_write
.addr
>> 1,
137 state
->log_reg_write
.data
);
139 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx64
")\n", pc
, insn
.bits() & mask
);
142 state
->log_reg_write
.addr
= 0;
146 inline void processor_t::update_histogram(size_t pc
)
148 #ifdef RISCV_ENABLE_HISTOGRAM
149 size_t idx
= pc
>> 2;
154 static reg_t
execute_insn(processor_t
* p
, reg_t pc
, insn_fetch_t fetch
)
156 reg_t npc
= fetch
.func(p
, fetch
.insn
, pc
);
157 commit_log(p
->get_state(), pc
, fetch
.insn
);
158 p
->update_histogram(pc
);
162 static void update_timer(state_t
* state
, size_t instret
)
164 uint64_t count0
= (uint64_t)(uint32_t)state
->scount
;
165 state
->scount
+= instret
;
166 uint64_t before
= count0
- state
->stimecmp
;
167 if (int64_t(before
^ (before
+ instret
)) < 0)
171 static size_t next_timer(state_t
* state
)
173 return state
->stimecmp
- (uint32_t)state
->scount
;
176 void processor_t::step(size_t n
)
182 if (unlikely(!run
|| !n
))
184 n
= std::min(n
, next_timer(&state
) | 1U);
192 while (instret
++ < n
)
194 insn_fetch_t fetch
= mmu
->load_insn(pc
);
196 pc
= execute_insn(this, pc
, fetch
);
199 else while (instret
< n
)
201 size_t idx
= _mmu
->icache_index(pc
);
202 auto ic_entry
= _mmu
->access_icache(pc
);
204 #define ICACHE_ACCESS(idx) { \
205 insn_fetch_t fetch = ic_entry->data; \
207 pc = execute_insn(this, pc, fetch); \
209 if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
210 if (unlikely(ic_entry->tag != pc)) break; \
220 pc
= take_trap(t
, pc
);
222 catch(serialize_t
& s
) {}
225 update_timer(&state
, instret
);
228 void processor_t::push_privilege_stack()
230 reg_t s
= state
.mstatus
;
231 s
= set_field(s
, MSTATUS_PRV2
, get_field(state
.mstatus
, MSTATUS_PRV1
));
232 s
= set_field(s
, MSTATUS_IE2
, get_field(state
.mstatus
, MSTATUS_IE1
));
233 s
= set_field(s
, MSTATUS_PRV1
, get_field(state
.mstatus
, MSTATUS_PRV
));
234 s
= set_field(s
, MSTATUS_IE1
, get_field(state
.mstatus
, MSTATUS_IE
));
235 s
= set_field(s
, MSTATUS_PRV
, PRV_M
);
236 s
= set_field(s
, MSTATUS_MPRV
, PRV_M
);
237 s
= set_field(s
, MSTATUS_IE
, 0);
238 set_csr(CSR_MSTATUS
, s
);
241 void processor_t::pop_privilege_stack()
243 reg_t s
= state
.mstatus
;
244 s
= set_field(s
, MSTATUS_PRV
, get_field(state
.mstatus
, MSTATUS_PRV1
));
245 s
= set_field(s
, MSTATUS_IE
, get_field(state
.mstatus
, MSTATUS_IE1
));
246 s
= set_field(s
, MSTATUS_PRV1
, get_field(state
.mstatus
, MSTATUS_PRV2
));
247 s
= set_field(s
, MSTATUS_IE1
, get_field(state
.mstatus
, MSTATUS_IE2
));
248 s
= set_field(s
, MSTATUS_PRV2
, PRV_U
);
249 s
= set_field(s
, MSTATUS_IE2
, 1);
250 set_csr(CSR_MSTATUS
, s
);
253 reg_t
processor_t::take_trap(trap_t
& t
, reg_t epc
)
256 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
259 reg_t tvec
= 0x40 * get_field(state
.mstatus
, MSTATUS_PRV
);
260 push_privilege_stack();
261 yield_load_reservation();
262 state
.mcause
= t
.cause();
264 t
.side_effects(&state
); // might set badvaddr etc.
268 void processor_t::deliver_ipi()
270 state
.mstatus
|= MSTATUS_MSIP
;
273 void processor_t::disasm(insn_t insn
)
275 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
276 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
277 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
280 static bool validate_priv(reg_t priv
)
282 return priv
== PRV_U
|| priv
== PRV_S
|| priv
== PRV_M
;
285 static bool validate_arch(reg_t arch
)
287 #ifdef RISCV_ENABLE_64BIT
288 if (arch
== UA_RV64
) return true;
290 return arch
== UA_RV32
;
293 static bool validate_vm(reg_t vm
)
295 // TODO: VM_SV32 support
296 #ifdef RISCV_ENABLE_64BIT
297 if (vm
== VM_SV43
) return true;
299 return vm
== VM_MBARE
;
302 void processor_t::set_csr(int which
, reg_t val
)
308 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
312 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
316 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
317 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
322 state
.scount
= val
; break;
326 state
.scount
= (val
<< 32) | (uint32_t)state
.scount
;
330 if ((val
^ state
.mstatus
) & (MSTATUS_VM
| MSTATUS_PRV
| MSTATUS_MPRV
))
333 reg_t mask
= MSTATUS_SSIP
| MSTATUS_MSIP
| MSTATUS_IE
| MSTATUS_IE1
334 | MSTATUS_IE2
| MSTATUS_IE3
| MSTATUS_STIE
;
335 #ifdef RISCV_ENABLE_FPU
340 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
342 if (validate_vm(get_field(val
, MSTATUS_VM
)))
343 state
.mstatus
= (state
.mstatus
& ~MSTATUS_VM
) | (val
& MSTATUS_VM
);
344 if (validate_priv(get_field(val
, MSTATUS_MPRV
)))
345 state
.mstatus
= (state
.mstatus
& ~MSTATUS_MPRV
) | (val
& MSTATUS_MPRV
);
346 if (validate_priv(get_field(val
, MSTATUS_PRV
)))
347 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV
) | (val
& MSTATUS_PRV
);
348 if (validate_priv(get_field(val
, MSTATUS_PRV1
)))
349 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV1
) | (val
& MSTATUS_PRV1
);
350 if (validate_priv(get_field(val
, MSTATUS_PRV2
)))
351 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV2
) | (val
& MSTATUS_PRV2
);
352 if (validate_priv(get_field(val
, MSTATUS_PRV3
)))
353 state
.mstatus
= (state
.mstatus
& ~MSTATUS_PRV3
) | (val
& MSTATUS_PRV3
);
356 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
357 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
358 #ifndef RISCV_ENABLE_64BIT
359 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
361 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
363 if (validate_arch(get_field(val
, MSTATUS64_UA
)))
364 state
.mstatus
= (state
.mstatus
& ~MSTATUS64_UA
) | (val
& MSTATUS64_UA
);
365 if (validate_arch(get_field(val
, MSTATUS64_SA
)))
366 state
.mstatus
= (state
.mstatus
& ~MSTATUS64_SA
) | (val
& MSTATUS64_SA
);
367 switch (get_field(state
.mstatus
, MSTATUS_PRV
)) {
368 case PRV_U
: if (get_field(state
.mstatus
, MSTATUS64_UA
)) xlen
= 64; break;
369 case PRV_S
: if (get_field(state
.mstatus
, MSTATUS64_SA
)) xlen
= 64; break;
370 case PRV_M
: xlen
= 64; break;
378 reg_t ms
= state
.mstatus
;
379 ms
= set_field(ms
, MSTATUS_SSIP
, get_field(val
, SSTATUS_SIP
));
380 ms
= set_field(ms
, MSTATUS_IE
, get_field(val
, SSTATUS_IE
));
381 ms
= set_field(ms
, MSTATUS_IE1
, get_field(val
, SSTATUS_PIE
));
382 ms
= set_field(ms
, MSTATUS_PRV1
, get_field(val
, SSTATUS_PS
));
383 ms
= set_field(ms
, MSTATUS64_UA
, get_field(val
, SSTATUS_UA
));
384 ms
= set_field(ms
, MSTATUS_STIE
, get_field(val
, SSTATUS_TIE
));
385 ms
= set_field(ms
, MSTATUS_FS
, get_field(val
, SSTATUS_FS
));
386 ms
= set_field(ms
, MSTATUS_XS
, get_field(val
, SSTATUS_XS
));
387 return set_csr(CSR_MSTATUS
, ms
);
389 case CSR_SEPC
: state
.sepc
= val
; break;
390 case CSR_STVEC
: state
.stvec
= val
& ~3; break;
394 state
.stimecmp
= val
;
396 case CSR_SPTBR
: state
.sptbr
= val
& ~(PGSIZE
-1); break;
397 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
398 case CSR_MEPC
: state
.mepc
= val
; break;
399 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
400 case CSR_MCAUSE
: state
.mcause
= val
; break;
401 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
402 case CSR_SEND_IPI
: sim
->send_ipi(val
); break;
404 if (state
.tohost
== 0)
407 case CSR_FROMHOST
: state
.fromhost
= val
; break;
411 reg_t
processor_t::get_csr(int which
)
423 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
441 return state
.scount
>> 32;
445 ss
= set_field(ss
, SSTATUS_SIP
, get_field(state
.mstatus
, MSTATUS_SSIP
));
446 ss
= set_field(ss
, SSTATUS_IE
, get_field(state
.mstatus
, MSTATUS_IE
));
447 ss
= set_field(ss
, SSTATUS_PIE
, get_field(state
.mstatus
, MSTATUS_IE1
));
448 ss
= set_field(ss
, SSTATUS_PS
, get_field(state
.mstatus
, MSTATUS_PRV1
));
449 ss
= set_field(ss
, SSTATUS_UA
, get_field(state
.mstatus
, MSTATUS64_UA
));
450 ss
= set_field(ss
, SSTATUS_TIE
, get_field(state
.mstatus
, MSTATUS_STIE
));
451 ss
= set_field(ss
, SSTATUS_TIP
, state
.stip
);
452 ss
= set_field(ss
, SSTATUS_FS
, get_field(state
.mstatus
, MSTATUS_FS
));
453 ss
= set_field(ss
, SSTATUS_XS
, get_field(state
.mstatus
, MSTATUS_XS
));
454 if (get_field(state
.mstatus
, MSTATUS64_SD
))
455 ss
= set_field(ss
, (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
), 1);
458 case CSR_SEPC
: return state
.sepc
;
459 case CSR_SBADADDR
: return state
.sbadaddr
;
460 case CSR_STVEC
: return state
.stvec
;
461 case CSR_STIMECMP
: return state
.stimecmp
;
463 if (xlen
== 32 && (state
.scause
>> 63) != 0)
464 return state
.scause
| ((reg_t
)1 << 31);
466 case CSR_SPTBR
: return state
.sptbr
;
467 case CSR_SASID
: return 0;
468 case CSR_SSCRATCH
: return state
.sscratch
;
469 case CSR_MSTATUS
: return state
.mstatus
;
470 case CSR_MEPC
: return state
.mepc
;
471 case CSR_MSCRATCH
: return state
.mscratch
;
472 case CSR_MCAUSE
: return state
.mcause
;
473 case CSR_MBADADDR
: return state
.mbadaddr
;
475 sim
->get_htif()->tick(); // not necessary, but faster
478 sim
->get_htif()->tick(); // not necessary, but faster
479 return state
.fromhost
;
480 case CSR_SEND_IPI
: return 0;
481 case CSR_HARTID
: return id
;
500 throw trap_illegal_instruction();
503 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
505 throw trap_illegal_instruction();
508 insn_func_t
processor_t::decode_insn(insn_t insn
)
510 size_t mask
= opcode_map
.size()-1;
511 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
513 while ((insn
.bits() & desc
->mask
) != desc
->match
)
516 return xlen
== 64 ? desc
->rv64
: desc
->rv32
;
519 void processor_t::register_insn(insn_desc_t desc
)
521 assert(desc
.mask
& 1);
522 instructions
.push_back(desc
);
525 void processor_t::build_opcode_map()
528 for (auto& inst
: instructions
)
529 while ((inst
.mask
& buckets
) != buckets
)
534 decltype(insn_desc_t::match
) mask
;
535 cmp(decltype(mask
) mask
) : mask(mask
) {}
536 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
537 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
538 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
539 return lhs
.match
< rhs
.match
;
542 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
544 opcode_map
.resize(buckets
);
545 opcode_store
.resize(instructions
.size() + 1);
548 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
550 opcode_map
[b
] = &opcode_store
[j
];
551 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
552 opcode_store
[j
++] = instructions
[i
++];
555 assert(j
== opcode_store
.size()-1);
556 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
557 opcode_store
[j
].rv32
= &illegal_instruction
;
558 opcode_store
[j
].rv64
= &illegal_instruction
;
561 void processor_t::register_extension(extension_t
* x
)
563 for (auto insn
: x
->get_instructions())
566 for (auto disasm_insn
: x
->get_disasms())
567 disassembler
->add_insn(disasm_insn
);
569 throw std::logic_error("only one extension may be registered");
571 x
->set_processor(this);