riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "sim.h"
   8 #include "htif.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
  23   : sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
  24     id(_id), run(false), debug(false), serialized(false)
  25 {
  26   reset(true);
  27   mmu->set_processor(this);
  28
  29   #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
  30   #include "encoding.h"
  31   #undef DECLARE_INSN
  32   build_opcode_map();
  33 }
  34
  35 processor_t::~processor_t()
  36 {
  37 #ifdef RISCV_ENABLE_HISTOGRAM
  38   if (histogram_enabled)
  39   {
  40     fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
  41     for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
  42       fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
  43     }
  44   }
  45 #endif
  46
  47   delete disassembler;
  48 }
  49
  50 void state_t::reset()
  51 {
  52   memset(this, 0, sizeof(*this));
  53   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
  54   mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
  55   mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
  56 #ifdef RISCV_ENABLE_64BIT
  57   mstatus = set_field(mstatus, MSTATUS64_UA, UA_RV64);
  58   mstatus = set_field(mstatus, MSTATUS64_SA, UA_RV64);
  59 #endif
  60   pc = 0x100;
  61   load_reservation = -1;
  62 }
  63
  64 void processor_t::set_debug(bool value)
  65 {
  66   debug = value;
  67   if (ext)
  68     ext->set_debug(value);
  69 }
  70
  71 void processor_t::set_histogram(bool value)
  72 {
  73   histogram_enabled = value;
  74 }
  75
  76 void processor_t::reset(bool value)
  77 {
  78   if (run == !value)
  79     return;
  80   run = !value;
  81
  82   state.reset(); // reset the core
  83   set_csr(CSR_MSTATUS, state.mstatus);
  84
  85   if (ext)
  86     ext->reset(); // reset the extension
  87 }
  88
  89 struct serialize_t {};
  90
  91 void processor_t::serialize()
  92 {
  93   if (serialized)
  94     serialized = false;
  95   else
  96     serialized = true, throw serialize_t();
  97 }
  98
  99 void processor_t::raise_interrupt(reg_t which)
 100 {
 101   throw trap_t(((reg_t)1 << 63) | which);
 102 }
 103
 104 void processor_t::take_interrupt()
 105 {
 106   int priv = get_field(state.mstatus, MSTATUS_PRV);
 107   int ie = get_field(state.mstatus, MSTATUS_IE);
 108
 109   if (priv < PRV_M || (priv == PRV_M && ie)) {
 110     if (get_field(state.mstatus, MSTATUS_MSIP))
 111       raise_interrupt(IRQ_IPI);
 112
 113     if (state.fromhost != 0)
 114       raise_interrupt(IRQ_HOST);
 115   }
 116
 117   if (priv < PRV_S || (priv == PRV_S && ie)) {
 118     if (get_field(state.mstatus, MSTATUS_SSIP))
 119       raise_interrupt(IRQ_IPI);
 120
 121     if (state.stip && get_field(state.mstatus, MSTATUS_STIE))
 122       raise_interrupt(IRQ_TIMER);
 123   }
 124 }
 125
 126 static void commit_log(state_t* state, reg_t pc, insn_t insn)
 127 {
 128 #ifdef RISCV_ENABLE_COMMITLOG
 129   if (get_field(state->mstatus, MSTATUS_IE)) {
 130     uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
 131     if (state->log_reg_write.addr) {
 132       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
 133               pc,
 134               insn.bits() & mask,
 135               state->log_reg_write.addr & 1 ? 'f' : 'x',
 136               state->log_reg_write.addr >> 1,
 137               state->log_reg_write.data);
 138     } else {
 139       fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
 140     }
 141   }
 142   state->log_reg_write.addr = 0;
 143 #endif
 144 }
 145
 146 inline void processor_t::update_histogram(size_t pc)
 147 {
 148 #ifdef RISCV_ENABLE_HISTOGRAM
 149   size_t idx = pc >> 2;
 150   pc_histogram[idx]++;
 151 #endif
 152 }
 153
 154 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 155 {
 156   reg_t npc = fetch.func(p, fetch.insn, pc);
 157   commit_log(p->get_state(), pc, fetch.insn);
 158   p->update_histogram(pc);
 159   return npc;
 160 }
 161
 162 static void update_timer(state_t* state, size_t instret)
 163 {
 164   uint64_t count0 = (uint64_t)(uint32_t)state->scount;
 165   state->scount += instret;
 166   uint64_t before = count0 - state->stimecmp;
 167   if (int64_t(before ^ (before + instret)) < 0)
 168     state->stip = true;
 169 }
 170
 171 static size_t next_timer(state_t* state)
 172 {
 173   return state->stimecmp - (uint32_t)state->scount;
 174 }
 175
 176 void processor_t::step(size_t n)
 177 {
 178   size_t instret = 0;
 179   reg_t pc = state.pc;
 180   mmu_t* _mmu = mmu;
 181
 182   if (unlikely(!run || !n))
 183     return;
 184   n = std::min(n, next_timer(&state) | 1U);
 185
 186   try
 187   {
 188     take_interrupt();
 189
 190     if (unlikely(debug))
 191     {
 192       while (instret++ < n)
 193       {
 194         insn_fetch_t fetch = mmu->load_insn(pc);
 195         disasm(fetch.insn);
 196         pc = execute_insn(this, pc, fetch);
 197       }
 198     }
 199     else while (instret < n)
 200     {
 201       size_t idx = _mmu->icache_index(pc);
 202       auto ic_entry = _mmu->access_icache(pc);
 203
 204       #define ICACHE_ACCESS(idx) { \
 205         insn_fetch_t fetch = ic_entry->data; \
 206         ic_entry++; \
 207         pc = execute_insn(this, pc, fetch); \
 208         instret++; \
 209         if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
 210         if (unlikely(ic_entry->tag != pc)) break; \
 211       }
 212
 213       switch (idx) {
 214         #include "icache.h"
 215       }
 216     }
 217   }
 218   catch(trap_t& t)
 219   {
 220     pc = take_trap(t, pc);
 221   }
 222   catch(serialize_t& s) {}
 223
 224   state.pc = pc;
 225   update_timer(&state, instret);
 226 }
 227
 228 void processor_t::push_privilege_stack()
 229 {
 230   reg_t s = state.mstatus;
 231   s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
 232   s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
 233   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
 234   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
 235   s = set_field(s, MSTATUS_PRV, PRV_M);
 236   s = set_field(s, MSTATUS_MPRV, PRV_M);
 237   s = set_field(s, MSTATUS_IE, 0);
 238   set_csr(CSR_MSTATUS, s);
 239 }
 240
 241 void processor_t::pop_privilege_stack()
 242 {
 243   reg_t s = state.mstatus;
 244   s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
 245   s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
 246   s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
 247   s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
 248   s = set_field(s, MSTATUS_PRV2, PRV_U);
 249   s = set_field(s, MSTATUS_IE2, 1);
 250   set_csr(CSR_MSTATUS, s);
 251 }
 252
 253 reg_t processor_t::take_trap(trap_t& t, reg_t epc)
 254 {
 255   if (debug)
 256     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 257             id, t.name(), epc);
 258
 259   reg_t tvec = 0x40 * get_field(state.mstatus, MSTATUS_PRV);
 260   push_privilege_stack();
 261   yield_load_reservation();
 262   state.mcause = t.cause();
 263   state.mepc = epc;
 264   t.side_effects(&state); // might set badvaddr etc.
 265   return tvec;
 266 }
 267
 268 void processor_t::deliver_ipi()
 269 {
 270   state.mstatus |= MSTATUS_MSIP;
 271 }
 272
 273 void processor_t::disasm(insn_t insn)
 274 {
 275   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 276   fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 277           id, state.pc, bits, disassembler->disassemble(insn).c_str());
 278 }
 279
 280 static bool validate_priv(reg_t priv)
 281 {
 282   return priv == PRV_U || priv == PRV_S || priv == PRV_M;
 283 }
 284
 285 static bool validate_arch(reg_t arch)
 286 {
 287 #ifdef RISCV_ENABLE_64BIT
 288   if (arch == UA_RV64) return true;
 289 #endif
 290   return arch == UA_RV32;
 291 }
 292
 293 static bool validate_vm(reg_t vm)
 294 {
 295   // TODO: VM_SV32 support
 296 #ifdef RISCV_ENABLE_64BIT
 297   if (vm == VM_SV43) return true;
 298 #endif
 299   return vm == VM_MBARE;
 300 }
 301
 302 void processor_t::set_csr(int which, reg_t val)
 303 {
 304   switch (which)
 305   {
 306     case CSR_FFLAGS:
 307       dirty_fp_state;
 308       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 309       break;
 310     case CSR_FRM:
 311       dirty_fp_state;
 312       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 313       break;
 314     case CSR_FCSR:
 315       dirty_fp_state;
 316       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 317       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 318       break;
 319     case CSR_SCYCLE:
 320     case CSR_STIME:
 321     case CSR_SINSTRET:
 322       state.scount = val; break;
 323     case CSR_SCYCLEH:
 324     case CSR_STIMEH:
 325     case CSR_SINSTRETH:
 326       state.scount = (val << 32) | (uint32_t)state.scount;
 327       break;
 328     case CSR_MSTATUS:
 329     {
 330       if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_MPRV))
 331         mmu->flush_tlb();
 332
 333       reg_t mask = MSTATUS_SSIP | MSTATUS_MSIP | MSTATUS_IE | MSTATUS_IE1
 334                    | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE;
 335 #ifdef RISCV_ENABLE_FPU
 336       mask |= MSTATUS_FS;
 337 #endif
 338       if (ext)
 339         mask |= MSTATUS_XS;
 340       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 341
 342       if (validate_vm(get_field(val, MSTATUS_VM)))
 343         state.mstatus = (state.mstatus & ~MSTATUS_VM) | (val & MSTATUS_VM);
 344       if (validate_priv(get_field(val, MSTATUS_MPRV)))
 345         state.mstatus = (state.mstatus & ~MSTATUS_MPRV) | (val & MSTATUS_MPRV);
 346       if (validate_priv(get_field(val, MSTATUS_PRV)))
 347         state.mstatus = (state.mstatus & ~MSTATUS_PRV) | (val & MSTATUS_PRV);
 348       if (validate_priv(get_field(val, MSTATUS_PRV1)))
 349         state.mstatus = (state.mstatus & ~MSTATUS_PRV1) | (val & MSTATUS_PRV1);
 350       if (validate_priv(get_field(val, MSTATUS_PRV2)))
 351         state.mstatus = (state.mstatus & ~MSTATUS_PRV2) | (val & MSTATUS_PRV2);
 352       if (validate_priv(get_field(val, MSTATUS_PRV3)))
 353         state.mstatus = (state.mstatus & ~MSTATUS_PRV3) | (val & MSTATUS_PRV3);
 354       xlen = 32;
 355
 356       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 357       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 358 #ifndef RISCV_ENABLE_64BIT
 359       state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 360 #else
 361       state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 362
 363       if (validate_arch(get_field(val, MSTATUS64_UA)))
 364         state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA);
 365       if (validate_arch(get_field(val, MSTATUS64_SA)))
 366         state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA);
 367       switch (get_field(state.mstatus, MSTATUS_PRV)) {
 368         case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break;
 369         case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break;
 370         case PRV_M: xlen = 64; break;
 371         default: abort();
 372       }
 373 #endif
 374       break;
 375     }
 376     case CSR_SSTATUS:
 377     {
 378       reg_t ms = state.mstatus;
 379       ms = set_field(ms, MSTATUS_SSIP, get_field(val, SSTATUS_SIP));
 380       ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
 381       ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
 382       ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
 383       ms = set_field(ms, MSTATUS64_UA, get_field(val, SSTATUS_UA));
 384       ms = set_field(ms, MSTATUS_STIE, get_field(val, SSTATUS_TIE));
 385       ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
 386       ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
 387       return set_csr(CSR_MSTATUS, ms);
 388     }
 389     case CSR_SEPC: state.sepc = val; break;
 390     case CSR_STVEC: state.stvec = val & ~3; break;
 391     case CSR_STIMECMP:
 392       serialize();
 393       state.stip = false;
 394       state.stimecmp = val;
 395       break;
 396     case CSR_SPTBR: state.sptbr = val & ~(PGSIZE-1); break;
 397     case CSR_SSCRATCH: state.sscratch = val; break;
 398     case CSR_MEPC: state.mepc = val; break;
 399     case CSR_MSCRATCH: state.mscratch = val; break;
 400     case CSR_MCAUSE: state.mcause = val; break;
 401     case CSR_MBADADDR: state.mbadaddr = val; break;
 402     case CSR_SEND_IPI: sim->send_ipi(val); break;
 403     case CSR_TOHOST:
 404       if (state.tohost == 0)
 405         state.tohost = val;
 406       break;
 407     case CSR_FROMHOST: state.fromhost = val; break;
 408   }
 409 }
 410
 411 reg_t processor_t::get_csr(int which)
 412 {
 413   switch (which)
 414   {
 415     case CSR_FFLAGS:
 416       require_fp;
 417       return state.fflags;
 418     case CSR_FRM:
 419       require_fp;
 420       return state.frm;
 421     case CSR_FCSR:
 422       require_fp;
 423       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 424     case CSR_CYCLE:
 425     case CSR_TIME:
 426     case CSR_INSTRET:
 427     case CSR_SCYCLE:
 428     case CSR_STIME:
 429     case CSR_SINSTRET:
 430       serialize();
 431       return state.scount;
 432     case CSR_CYCLEH:
 433     case CSR_TIMEH:
 434     case CSR_INSTRETH:
 435     case CSR_SCYCLEH:
 436     case CSR_STIMEH:
 437     case CSR_SINSTRETH:
 438       if (xlen == 64)
 439         break;
 440       serialize();
 441       return state.scount >> 32;
 442     case CSR_SSTATUS:
 443     {
 444       reg_t ss = 0;
 445       ss = set_field(ss, SSTATUS_SIP, get_field(state.mstatus, MSTATUS_SSIP));
 446       ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
 447       ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
 448       ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
 449       ss = set_field(ss, SSTATUS_UA, get_field(state.mstatus, MSTATUS64_UA));
 450       ss = set_field(ss, SSTATUS_TIE, get_field(state.mstatus, MSTATUS_STIE));
 451       ss = set_field(ss, SSTATUS_TIP, state.stip);
 452       ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
 453       ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
 454       if (get_field(state.mstatus, MSTATUS64_SD))
 455         ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
 456       return ss;
 457     }
 458     case CSR_SEPC: return state.sepc;
 459     case CSR_SBADADDR: return state.sbadaddr;
 460     case CSR_STVEC: return state.stvec;
 461     case CSR_STIMECMP: return state.stimecmp;
 462     case CSR_SCAUSE:
 463       if (xlen == 32 && (state.scause >> 63) != 0)
 464         return state.scause | ((reg_t)1 << 31);
 465       return state.scause;
 466     case CSR_SPTBR: return state.sptbr;
 467     case CSR_SASID: return 0;
 468     case CSR_SSCRATCH: return state.sscratch;
 469     case CSR_MSTATUS: return state.mstatus;
 470     case CSR_MEPC: return state.mepc;
 471     case CSR_MSCRATCH: return state.mscratch;
 472     case CSR_MCAUSE: return state.mcause;
 473     case CSR_MBADADDR: return state.mbadaddr;
 474     case CSR_TOHOST:
 475       sim->get_htif()->tick(); // not necessary, but faster
 476       return state.tohost;
 477     case CSR_FROMHOST:
 478       sim->get_htif()->tick(); // not necessary, but faster
 479       return state.fromhost;
 480     case CSR_SEND_IPI: return 0;
 481     case CSR_HARTID: return id;
 482     case CSR_UARCH0:
 483     case CSR_UARCH1:
 484     case CSR_UARCH2:
 485     case CSR_UARCH3:
 486     case CSR_UARCH4:
 487     case CSR_UARCH5:
 488     case CSR_UARCH6:
 489     case CSR_UARCH7:
 490     case CSR_UARCH8:
 491     case CSR_UARCH9:
 492     case CSR_UARCH10:
 493     case CSR_UARCH11:
 494     case CSR_UARCH12:
 495     case CSR_UARCH13:
 496     case CSR_UARCH14:
 497     case CSR_UARCH15:
 498       return 0;
 499   }
 500   throw trap_illegal_instruction();
 501 }
 502
 503 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 504 {
 505   throw trap_illegal_instruction();
 506 }
 507
 508 insn_func_t processor_t::decode_insn(insn_t insn)
 509 {
 510   size_t mask = opcode_map.size()-1;
 511   insn_desc_t* desc = opcode_map[insn.bits() & mask];
 512
 513   while ((insn.bits() & desc->mask) != desc->match)
 514     desc++;
 515
 516   return xlen == 64 ? desc->rv64 : desc->rv32;
 517 }
 518
 519 void processor_t::register_insn(insn_desc_t desc)
 520 {
 521   assert(desc.mask & 1);
 522   instructions.push_back(desc);
 523 }
 524
 525 void processor_t::build_opcode_map()
 526 {
 527   size_t buckets = -1;
 528   for (auto& inst : instructions)
 529     while ((inst.mask & buckets) != buckets)
 530       buckets /= 2;
 531   buckets++;
 532
 533   struct cmp {
 534     decltype(insn_desc_t::match) mask;
 535     cmp(decltype(mask) mask) : mask(mask) {}
 536     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 537       if ((lhs.match & mask) != (rhs.match & mask))
 538         return (lhs.match & mask) < (rhs.match & mask);
 539       return lhs.match < rhs.match;
 540     }
 541   };
 542   std::sort(instructions.begin(), instructions.end(), cmp(buckets-1));
 543
 544   opcode_map.resize(buckets);
 545   opcode_store.resize(instructions.size() + 1);
 546
 547   size_t j = 0;
 548   for (size_t b = 0, i = 0; b < buckets; b++)
 549   {
 550     opcode_map[b] = &opcode_store[j];
 551     while (i < instructions.size() && b == (instructions[i].match & (buckets-1)))
 552       opcode_store[j++] = instructions[i++];
 553   }
 554
 555   assert(j == opcode_store.size()-1);
 556   opcode_store[j].match = opcode_store[j].mask = 0;
 557   opcode_store[j].rv32 = &illegal_instruction;
 558   opcode_store[j].rv64 = &illegal_instruction;
 559 }
 560
 561 void processor_t::register_extension(extension_t* x)
 562 {
 563   for (auto insn : x->get_instructions())
 564     register_insn(insn);
 565   build_opcode_map();
 566   for (auto disasm_insn : x->get_disasms())
 567     disassembler->add_insn(disasm_insn);
 568   if (ext != NULL)
 569     throw std::logic_error("only one extension may be registered");
 570   ext = x;
 571   x->set_processor(this);
 572 }