1 // See LICENSE for license details.
23 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
24 : sim(_sim
), mmu(_mmu
), ext(NULL
), disassembler(new disassembler_t
),
25 id(_id
), run(false), debug(false)
28 mmu
->set_processor(this);
30 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
36 processor_t::~processor_t()
43 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
44 // is in supervisor mode, and in 64-bit mode, if supported, with traps
45 // and virtual memory disabled.
46 sr
= SR_S
| SR_S64
| SR_U64
;
49 // the following state is undefined upon boot-up,
50 // but we zero it for determinism
68 load_reservation
= -1;
71 void processor_t::set_debug(bool value
)
75 ext
->set_debug(value
);
78 void processor_t::reset(bool value
)
84 state
.reset(); // reset the core
85 set_pcr(CSR_STATUS
, state
.sr
);
88 ext
->reset(); // reset the extension
91 void processor_t::take_interrupt()
93 uint32_t interrupts
= (state
.sr
& SR_IP
) >> SR_IP_SHIFT
;
94 interrupts
&= (state
.sr
& SR_IM
) >> SR_IM_SHIFT
;
96 if (interrupts
&& (state
.sr
& SR_EI
))
97 for (int i
= 0; ; i
++, interrupts
>>= 1)
99 throw trap_t((1ULL << ((state
.sr
& SR_S64
) ? 63 : 31)) + i
);
102 static void commit_log(state_t
* state
, insn_t insn
)
104 #ifdef RISCV_ENABLE_COMMITLOG
105 if (state
->sr
& SR_EI
) {
106 if (state
->log_reg_write
.addr
) {
107 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx32
") %c%2u 0x%016" PRIx64
"\n",
108 state
->pc
, insn
.bits(),
109 state
->log_reg_write
.addr
& 1 ? 'f' : 'x',
110 state
->log_reg_write
.addr
>> 1, state
->log_reg_write
.data
);
113 fprintf(stderr
, "0x%016" PRIx64
" (0x%08" PRIx32
")\n",
114 state
->pc
, insn
.bits());
117 state
->log_reg_write
.addr
= 0;
121 static inline void execute_insn(processor_t
* p
, state_t
* st
, insn_fetch_t fetch
)
123 reg_t npc
= fetch
.func(p
, fetch
.insn
.insn
, st
->pc
);
124 commit_log(st
, fetch
.insn
.insn
);
128 void processor_t::step(size_t n0
)
134 auto count32
= decltype(state
.compare
)(state
.count
);
135 bool count_le_compare
= count32
<= state
.compare
;
136 ssize_t n
= std::min(ssize_t(n0
), ssize_t((state
.compare
- count32
) | 1));
142 if (debug
) // print out instructions as we go
144 for (ssize_t i
= 0; i
< n
; state
.count
++, i
++)
146 insn_fetch_t fetch
= mmu
->load_insn(state
.pc
);
147 disasm(fetch
.insn
.insn
);
148 execute_insn(this, &state
, fetch
);
153 size_t idx
= (state
.pc
/ sizeof(insn_t
)) % ICACHE_SIZE
;
154 auto ic_entry
= _mmu
->access_icache(state
.pc
), ic_entry_init
= ic_entry
;
156 #define ICACHE_ACCESS(idx) { \
157 insn_fetch_t fetch = ic_entry->data; \
159 execute_insn(this, &state, fetch); \
160 if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \
165 ICACHE_SWITCH
; // auto-generated into icache.h
168 size_t i
= ic_entry
- ic_entry_init
;
178 bool count_ge_compare
=
179 uint64_t(n
) + decltype(state
.compare
)(state
.count
) >= state
.compare
;
180 if (count_le_compare
&& count_ge_compare
)
181 set_interrupt(IRQ_TIMER
, true);
184 void processor_t::take_trap(trap_t
& t
)
187 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
188 id
, t
.name(), state
.pc
);
190 // switch to supervisor, set previous supervisor bit, disable interrupts
191 set_pcr(CSR_STATUS
, (((state
.sr
& ~SR_EI
) | SR_S
) & ~SR_PS
& ~SR_PEI
) |
192 ((state
.sr
& SR_S
) ? SR_PS
: 0) |
193 ((state
.sr
& SR_EI
) ? SR_PEI
: 0));
195 yield_load_reservation();
196 state
.cause
= t
.cause();
197 state
.epc
= state
.pc
;
198 state
.pc
= state
.evec
;
200 t
.side_effects(&state
); // might set badvaddr etc.
203 void processor_t::deliver_ipi()
206 set_pcr(CSR_CLEAR_IPI
, 1);
209 void processor_t::disasm(insn_t insn
)
211 // the disassembler is stateless, so we share it
212 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx32
") %s\n",
213 id
, state
.pc
, insn
.bits(), disassembler
->disassemble(insn
).c_str());
216 reg_t
processor_t::set_pcr(int which
, reg_t val
)
218 reg_t old_pcr
= get_pcr(which
);
223 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
226 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
229 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
230 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
233 state
.sr
= (val
& ~SR_IP
) | (state
.sr
& SR_IP
);
234 #ifndef RISCV_ENABLE_64BIT
235 state
.sr
&= ~(SR_S64
| SR_U64
);
237 #ifndef RISCV_ENABLE_FPU
242 state
.sr
&= ~SR_ZERO
;
243 rv64
= (state
.sr
& SR_S
) ? (state
.sr
& SR_S64
) : (state
.sr
& SR_U64
);
250 state
.evec
= val
& ~3;
256 state
.count
= (val
<< 32) | (uint32_t)state
.count
;
259 set_interrupt(IRQ_TIMER
, false);
263 state
.ptbr
= val
& ~(PGSIZE
-1);
269 set_interrupt(IRQ_IPI
, val
& 1);
278 if (state
.tohost
== 0)
289 void processor_t::set_fromhost(reg_t val
)
291 set_interrupt(IRQ_HOST
, val
!= 0);
292 state
.fromhost
= val
;
295 reg_t
processor_t::get_pcr(int which
)
307 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
313 return state
.badvaddr
;
327 return state
.count
>> 32;
329 return state
.compare
;
351 sim
->get_htif()->tick(); // not necessary, but faster
354 sim
->get_htif()->tick(); // not necessary, but faster
355 return state
.fromhost
;
374 throw trap_illegal_instruction();
377 void processor_t::set_interrupt(int which
, bool on
)
379 uint32_t mask
= (1 << (which
+ SR_IP_SHIFT
)) & SR_IP
;
386 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
388 throw trap_illegal_instruction();
391 insn_func_t
processor_t::decode_insn(insn_t insn
)
393 size_t mask
= opcode_map
.size()-1;
394 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
396 while ((insn
.bits() & desc
->mask
) != desc
->match
)
399 return rv64
? desc
->rv64
: desc
->rv32
;
402 void processor_t::register_insn(insn_desc_t desc
)
404 assert(desc
.mask
& 1);
405 instructions
.push_back(desc
);
408 void processor_t::build_opcode_map()
411 for (auto& inst
: instructions
)
412 while ((inst
.mask
& buckets
) != buckets
)
417 decltype(insn_desc_t::match
) mask
;
418 cmp(decltype(mask
) mask
) : mask(mask
) {}
419 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
420 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
421 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
422 return lhs
.match
< rhs
.match
;
425 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
427 opcode_map
.resize(buckets
);
428 opcode_store
.resize(instructions
.size() + 1);
431 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
433 opcode_map
[b
] = &opcode_store
[j
];
434 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
435 opcode_store
[j
++] = instructions
[i
++];
438 assert(j
== opcode_store
.size()-1);
439 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
440 opcode_store
[j
].rv32
= &illegal_instruction
;
441 opcode_store
[j
].rv64
= &illegal_instruction
;
444 void processor_t::register_extension(extension_t
* x
)
446 for (auto insn
: x
->get_instructions())
449 for (auto disasm_insn
: x
->get_disasms())
450 disassembler
->add_insn(disasm_insn
);
452 throw std::logic_error("only one extension may be registered");
454 x
->set_processor(this);