1 // See LICENSE for license details.
20 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
)
21 : sim(_sim
), mmu(_mmu
), ext(NULL
), disassembler(new disassembler_t
),
22 id(_id
), run(false), debug(false)
25 mmu
->set_processor(this);
27 #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
33 processor_t::~processor_t()
39 // the ISA guarantees on boot that the PC is 0x2000 and the the processor
40 // is in supervisor mode, and in 64-bit mode, if supported, with traps
41 // and virtual memory disabled.
45 // the following state is undefined upon boot-up,
46 // but we zero it for determinism
64 load_reservation
= -1;
67 void processor_t::set_debug(bool value
)
71 ext
->set_debug(value
);
74 void processor_t::reset(bool value
)
80 state
.reset(); // reset the core
81 set_pcr(CSR_STATUS
, state
.sr
);
84 ext
->reset(); // reset the extension
87 void processor_t::take_interrupt()
89 uint32_t interrupts
= (state
.sr
& SR_IP
) >> SR_IP_SHIFT
;
90 interrupts
&= (state
.sr
& SR_IM
) >> SR_IM_SHIFT
;
92 if (interrupts
&& (state
.sr
& SR_EI
))
93 for (int i
= 0; ; i
++, interrupts
>>= 1)
95 throw trap_t((1ULL << ((state
.sr
& SR_S64
) ? 63 : 31)) + i
);
98 void processor_t::step(size_t n
)
104 auto count32
= decltype(state
.compare
)(state
.count
);
105 bool count_le_compare
= count32
<= state
.compare
;
106 n
= std::min(n
, size_t(state
.compare
- count32
) | 1);
112 // execute_insn fetches and executes one instruction
113 #define execute_insn(noisy) \
115 insn_fetch_t fetch = mmu->load_insn(state.pc); \
116 if(noisy) disasm(fetch.insn.insn); \
117 state.pc = fetch.func(this, fetch.insn.insn, state.pc); \
121 // special execute_insn for commit log dumping
122 #ifdef RISCV_ENABLE_COMMITLOG
123 //static disassembler disasmblr;
125 #define execute_insn(noisy) \
127 insn_fetch_t fetch = _mmu->load_insn(state.pc); \
128 if(noisy) disasm(fetch.insn.insn); \
129 bool in_spvr = state.sr & SR_S; \
130 if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state.pc, fetch.insn.insn.bits()); \
131 /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s ", state.pc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
132 state.pc = fetch.func(this, fetch.insn.insn, state.pc); \
136 if (debug
) // print out instructions as we go
138 for (size_t i
= 0; i
< n
; state
.count
++, i
++)
143 size_t idx
= (state
.pc
/ sizeof(insn_t
)) % ICACHE_SIZE
;
144 auto ic_entry_init
= &_mmu
->icache
[idx
], ic_entry
= ic_entry_init
;
146 #define update_count() { \
147 size_t i = ic_entry - ic_entry_init; \
152 #define ICACHE_ACCESS(idx) { \
153 insn_t insn = ic_entry->data.insn.insn; \
154 insn_func_t func = ic_entry->data.func; \
155 if (unlikely(ic_entry->tag != state.pc)) break; \
157 state.pc = func(this, insn, state.pc); }
159 switch (idx
) while (true)
163 ic_entry_init
= ic_entry
= &_mmu
->icache
[0];
166 _mmu
->access_icache(state
.pc
);
175 bool count_ge_compare
=
176 uint64_t(n
) + decltype(state
.compare
)(state
.count
) >= state
.compare
;
177 if (count_le_compare
&& count_ge_compare
)
178 set_interrupt(IRQ_TIMER
, true);
181 void processor_t::take_trap(trap_t
& t
)
184 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
185 id
, t
.name(), state
.pc
);
187 // switch to supervisor, set previous supervisor bit, disable interrupts
188 set_pcr(CSR_STATUS
, (((state
.sr
& ~SR_EI
) | SR_S
) & ~SR_PS
& ~SR_PEI
) |
189 ((state
.sr
& SR_S
) ? SR_PS
: 0) |
190 ((state
.sr
& SR_EI
) ? SR_PEI
: 0));
192 yield_load_reservation();
193 state
.cause
= t
.cause();
194 state
.epc
= state
.pc
;
195 state
.pc
= state
.evec
;
197 t
.side_effects(&state
); // might set badvaddr etc.
200 void processor_t::deliver_ipi()
203 set_pcr(CSR_CLEAR_IPI
, 1);
206 void processor_t::disasm(insn_t insn
)
208 // the disassembler is stateless, so we share it
209 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx32
") %s\n",
210 id
, state
.pc
, insn
.bits(), disassembler
->disassemble(insn
).c_str());
213 reg_t
processor_t::set_pcr(int which
, reg_t val
)
215 reg_t old_pcr
= get_pcr(which
);
220 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
223 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
226 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
227 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
230 state
.sr
= (val
& ~SR_IP
) | (state
.sr
& SR_IP
);
231 #ifndef RISCV_ENABLE_64BIT
232 state
.sr
&= ~(SR_S64
| SR_U64
);
234 #ifndef RISCV_ENABLE_FPU
239 state
.sr
&= ~SR_ZERO
;
240 rv64
= (state
.sr
& SR_S
) ? (state
.sr
& SR_S64
) : (state
.sr
& SR_U64
);
247 state
.evec
= val
& ~3;
256 set_interrupt(IRQ_TIMER
, false);
260 state
.ptbr
= val
& ~(PGSIZE
-1);
266 set_interrupt(IRQ_IPI
, val
& 1);
275 if (state
.tohost
== 0)
286 void processor_t::set_fromhost(reg_t val
)
288 set_interrupt(IRQ_HOST
, val
!= 0);
289 state
.fromhost
= val
;
292 reg_t
processor_t::get_pcr(int which
)
301 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
307 return state
.badvaddr
;
316 return state
.compare
;
338 sim
->get_htif()->tick(); // not necessary, but faster
341 sim
->get_htif()->tick(); // not necessary, but faster
342 return state
.fromhost
;
344 throw trap_illegal_instruction();
348 void processor_t::set_interrupt(int which
, bool on
)
350 uint32_t mask
= (1 << (which
+ SR_IP_SHIFT
)) & SR_IP
;
357 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
359 throw trap_illegal_instruction();
362 insn_func_t
processor_t::decode_insn(insn_t insn
)
364 size_t mask
= opcode_map
.size()-1;
365 insn_desc_t
* desc
= opcode_map
[insn
.bits() & mask
];
367 while ((insn
.bits() & desc
->mask
) != desc
->match
)
370 return rv64
? desc
->rv64
: desc
->rv32
;
373 void processor_t::register_insn(insn_desc_t desc
)
375 assert(desc
.mask
& 1);
376 instructions
.push_back(desc
);
379 void processor_t::build_opcode_map()
382 for (auto& inst
: instructions
)
383 while ((inst
.mask
& buckets
) != buckets
)
388 decltype(insn_desc_t::match
) mask
;
389 cmp(decltype(mask
) mask
) : mask(mask
) {}
390 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
391 if ((lhs
.match
& mask
) != (rhs
.match
& mask
))
392 return (lhs
.match
& mask
) < (rhs
.match
& mask
);
393 return lhs
.match
< rhs
.match
;
396 std::sort(instructions
.begin(), instructions
.end(), cmp(buckets
-1));
398 opcode_map
.resize(buckets
);
399 opcode_store
.resize(instructions
.size() + 1);
402 for (size_t b
= 0, i
= 0; b
< buckets
; b
++)
404 opcode_map
[b
] = &opcode_store
[j
];
405 while (i
< instructions
.size() && b
== (instructions
[i
].match
& (buckets
-1)))
406 opcode_store
[j
++] = instructions
[i
++];
409 assert(j
== opcode_store
.size()-1);
410 opcode_store
[j
].match
= opcode_store
[j
].mask
= 0;
411 opcode_store
[j
].rv32
= &illegal_instruction
;
412 opcode_store
[j
].rv64
= &illegal_instruction
;
415 void processor_t::register_extension(extension_t
* x
)
417 for (auto insn
: x
->get_instructions())
420 for (auto disasm_insn
: x
->get_disasms())
421 disassembler
->add_insn(disasm_insn
);
423 throw std::logic_error("only one extension may be registered");
425 x
->set_processor(this);