1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
11 #include "debug_rom/debug_rom_defines.h"
15 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
29 struct commit_log_reg_t
49 ACTION_DEBUG_EXCEPTION
= MCONTROL_ACTION_DEBUG_EXCEPTION
,
50 ACTION_DEBUG_MODE
= MCONTROL_ACTION_DEBUG_MODE
,
51 ACTION_TRACE_START
= MCONTROL_ACTION_TRACE_START
,
52 ACTION_TRACE_STOP
= MCONTROL_ACTION_TRACE_STOP
,
53 ACTION_TRACE_EMIT
= MCONTROL_ACTION_TRACE_EMIT
58 MATCH_EQUAL
= MCONTROL_MATCH_EQUAL
,
59 MATCH_NAPOT
= MCONTROL_MATCH_NAPOT
,
60 MATCH_GE
= MCONTROL_MATCH_GE
,
61 MATCH_LT
= MCONTROL_MATCH_LT
,
62 MATCH_MASK_LOW
= MCONTROL_MATCH_MASK_LOW
,
63 MATCH_MASK_HIGH
= MCONTROL_MATCH_MASK_HIGH
73 mcontrol_action_t action
;
75 mcontrol_match_t match
;
85 // architectural state of a RISC-V hart
90 static const int num_triggers
= 4;
93 regfile_t
<reg_t
, NXPR
, true> XPR
;
94 regfile_t
<freg_t
, NFPR
, false> FPR
;
96 // control and status registers
97 reg_t prv
; // TODO: Can this be an enum instead?
121 mcontrol_t mcontrol
[num_triggers
];
122 reg_t tdata2
[num_triggers
];
126 bool serialized
; // whether timer CSRs are in a well-defined state
128 // When true, execute a single instruction and then enter debug mode. This
129 // can only be set by executing dret.
136 reg_t load_reservation
;
138 #ifdef RISCV_ENABLE_COMMITLOG
139 commit_log_reg_t log_reg_write
;
140 reg_t last_inst_priv
;
148 } trigger_operation_t
;
150 // Count number of contiguous 1 bits starting from the LSB.
151 static int cto(reg_t val
)
154 while ((val
& 1) == 1)
159 // this class represents one processor in a RISC-V machine.
160 class processor_t
: public abstract_device_t
163 processor_t(const char* isa
, sim_t
* sim
, uint32_t id
, bool halt_on_reset
=false);
166 void set_debug(bool value
);
167 void set_histogram(bool value
);
169 void step(size_t n
); // run for n cycles
170 void set_csr(int which
, reg_t val
);
171 reg_t
get_csr(int which
);
172 mmu_t
* get_mmu() { return mmu
; }
173 state_t
* get_state() { return &state
; }
174 extension_t
* get_extension() { return ext
; }
175 bool supports_extension(unsigned char ext
) {
176 if (ext
>= 'a' && ext
<= 'z') ext
+= 'A' - 'a';
177 return ext
>= 'A' && ext
<= 'Z' && ((isa
>> (ext
- 'A')) & 1);
179 void set_privilege(reg_t
);
180 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
181 void update_histogram(reg_t pc
);
182 const disassembler_t
* get_disassembler() { return disassembler
; }
184 void register_insn(insn_desc_t
);
185 void register_extension(extension_t
*);
187 // MMIO slave interface
188 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
189 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
191 // When true, display disassembly of each instruction that's executed.
193 // When true, take the slow simulation path.
195 bool halted() { return state
.dcsr
.cause
? true : false; }
197 // The unique debug rom address that this hart jumps to when entering debug
198 // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive.
199 uint32_t debug_rom_entry() {
200 fprintf(stderr
, "Debug_rom_entry called for id %d = %x\n", id
, DEBUG_ROM_ENTRY
+ 4*id
);
201 return DEBUG_ROM_ENTRY
+ 4 * id
;
204 // Return the index of a trigger that matched, or -1.
205 inline int trigger_match(trigger_operation_t operation
, reg_t address
, reg_t data
)
207 if (state
.dcsr
.cause
)
210 bool chain_ok
= true;
212 for (unsigned int i
= 0; i
< state
.num_triggers
; i
++) {
214 chain_ok
|= !state
.mcontrol
[i
].chain
;
218 if ((operation
== OPERATION_EXECUTE
&& !state
.mcontrol
[i
].execute
) ||
219 (operation
== OPERATION_STORE
&& !state
.mcontrol
[i
].store
) ||
220 (operation
== OPERATION_LOAD
&& !state
.mcontrol
[i
].load
) ||
221 (state
.prv
== PRV_M
&& !state
.mcontrol
[i
].m
) ||
222 (state
.prv
== PRV_H
&& !state
.mcontrol
[i
].h
) ||
223 (state
.prv
== PRV_S
&& !state
.mcontrol
[i
].s
) ||
224 (state
.prv
== PRV_U
&& !state
.mcontrol
[i
].u
)) {
229 if (state
.mcontrol
[i
].select
) {
235 // We need this because in 32-bit mode sometimes the PC bits get sign
241 switch (state
.mcontrol
[i
].match
) {
243 if (value
!= state
.tdata2
[i
])
248 reg_t mask
= ~((1 << cto(state
.tdata2
[i
])) - 1);
249 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
254 if (value
< state
.tdata2
[i
])
258 if (value
>= state
.tdata2
[i
])
263 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
264 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
268 case MATCH_MASK_HIGH
:
270 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
271 if (((value
>> (xlen
/2)) & mask
) != (state
.tdata2
[i
] & mask
))
277 if (!state
.mcontrol
[i
].chain
) {
285 void trigger_updated();
289 mmu_t
* mmu
; // main memory is always accessed via the mmu
291 disassembler_t
* disassembler
;
298 std::string isa_string
;
299 bool histogram_enabled
;
302 std::vector
<insn_desc_t
> instructions
;
303 std::map
<reg_t
,uint64_t> pc_histogram
;
305 static const size_t OPCODE_CACHE_SIZE
= 8191;
306 insn_desc_t opcode_cache
[OPCODE_CACHE_SIZE
];
308 void take_pending_interrupt() { take_interrupt(state
.mip
& state
.mie
); }
309 void take_interrupt(reg_t mask
); // take first enabled interrupt in mask
310 void take_trap(trap_t
& t
, reg_t epc
); // take an exception
311 void disasm(insn_t insn
); // disassemble and print an instruction
314 void enter_debug_mode(uint8_t cause
);
318 friend class clint_t
;
319 friend class extension_t
;
321 void parse_isa_string(const char* isa
);
322 void build_opcode_map();
323 void register_base_instructions();
324 insn_func_t
decode_insn(insn_t insn
);
327 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
329 #define REGISTER_INSN(proc, name, match, mask) \
330 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
331 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
332 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});