1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
14 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
28 struct commit_log_reg_t
48 ACTION_DEBUG_EXCEPTION
= MCONTROL_ACTION_DEBUG_EXCEPTION
,
49 ACTION_DEBUG_MODE
= MCONTROL_ACTION_DEBUG_MODE
,
50 ACTION_TRACE_START
= MCONTROL_ACTION_TRACE_START
,
51 ACTION_TRACE_STOP
= MCONTROL_ACTION_TRACE_STOP
,
52 ACTION_TRACE_EMIT
= MCONTROL_ACTION_TRACE_EMIT
57 MATCH_EQUAL
= MCONTROL_MATCH_EQUAL
,
58 MATCH_NAPOT
= MCONTROL_MATCH_NAPOT
,
59 MATCH_GE
= MCONTROL_MATCH_GE
,
60 MATCH_LT
= MCONTROL_MATCH_LT
,
61 MATCH_MASK_LOW
= MCONTROL_MATCH_MASK_LOW
,
62 MATCH_MASK_HIGH
= MCONTROL_MATCH_MASK_HIGH
72 mcontrol_action_t action
;
74 mcontrol_match_t match
;
84 // architectural state of a RISC-V hart
89 static const int num_triggers
= 4;
92 regfile_t
<reg_t
, NXPR
, true> XPR
;
93 regfile_t
<freg_t
, NFPR
, false> FPR
;
95 // control and status registers
96 reg_t prv
; // TODO: Can this be an enum instead?
108 uint32_t mucounteren
;
109 uint32_t mscounteren
;
120 mcontrol_t mcontrol
[num_triggers
];
121 reg_t tdata2
[num_triggers
];
125 bool serialized
; // whether timer CSRs are in a well-defined state
127 // When true, execute a single instruction and then enter debug mode. This
128 // can only be set by executing dret.
135 reg_t load_reservation
;
137 #ifdef RISCV_ENABLE_COMMITLOG
138 commit_log_reg_t log_reg_write
;
139 reg_t last_inst_priv
;
147 } trigger_operation_t
;
149 // Count number of contiguous 1 bits starting from the LSB.
150 static int cto(reg_t val
)
153 while ((val
& 1) == 1)
158 // this class represents one processor in a RISC-V machine.
159 class processor_t
: public abstract_device_t
162 processor_t(const char* isa
, sim_t
* sim
, uint32_t id
, bool halt_on_reset
=false);
165 void set_debug(bool value
);
166 void set_histogram(bool value
);
168 void step(size_t n
); // run for n cycles
169 void set_csr(int which
, reg_t val
);
170 void raise_interrupt(reg_t which
);
171 reg_t
get_csr(int which
);
172 mmu_t
* get_mmu() { return mmu
; }
173 state_t
* get_state() { return &state
; }
174 extension_t
* get_extension() { return ext
; }
175 bool supports_extension(unsigned char ext
) {
176 if (ext
>= 'a' && ext
<= 'z') ext
+= 'A' - 'a';
177 return ext
>= 'A' && ext
<= 'Z' && ((isa
>> (ext
- 'A')) & 1);
179 void set_privilege(reg_t
);
180 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
181 void update_histogram(reg_t pc
);
182 const disassembler_t
* get_disassembler() { return disassembler
; }
184 void register_insn(insn_desc_t
);
185 void register_extension(extension_t
*);
187 // MMIO slave interface
188 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
189 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
191 // When true, display disassembly of each instruction that's executed.
193 // When true, take the slow simulation path.
196 // Return the index of a trigger that matched, or -1.
197 inline int trigger_match(trigger_operation_t operation
, reg_t address
, reg_t data
)
199 if (state
.dcsr
.cause
)
202 bool chain_ok
= true;
204 for (unsigned int i
= 0; i
< state
.num_triggers
; i
++) {
206 chain_ok
|= !state
.mcontrol
[i
].chain
;
210 if ((operation
== OPERATION_EXECUTE
&& !state
.mcontrol
[i
].execute
) ||
211 (operation
== OPERATION_STORE
&& !state
.mcontrol
[i
].store
) ||
212 (operation
== OPERATION_LOAD
&& !state
.mcontrol
[i
].load
) ||
213 (state
.prv
== PRV_M
&& !state
.mcontrol
[i
].m
) ||
214 (state
.prv
== PRV_H
&& !state
.mcontrol
[i
].h
) ||
215 (state
.prv
== PRV_S
&& !state
.mcontrol
[i
].s
) ||
216 (state
.prv
== PRV_U
&& !state
.mcontrol
[i
].u
)) {
221 if (state
.mcontrol
[i
].select
) {
227 // We need this because in 32-bit mode sometimes the PC bits get sign
233 switch (state
.mcontrol
[i
].match
) {
235 if (value
!= state
.tdata2
[i
])
240 reg_t mask
= ~((1 << cto(state
.tdata2
[i
])) - 1);
241 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
246 if (value
< state
.tdata2
[i
])
250 if (value
>= state
.tdata2
[i
])
255 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
256 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
260 case MATCH_MASK_HIGH
:
262 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
263 if (((value
>> (xlen
/2)) & mask
) != (state
.tdata2
[i
] & mask
))
269 if (!state
.mcontrol
[i
].chain
) {
277 void trigger_updated();
281 mmu_t
* mmu
; // main memory is always accessed via the mmu
283 disassembler_t
* disassembler
;
289 std::string isa_string
;
290 bool histogram_enabled
;
293 std::vector
<insn_desc_t
> instructions
;
294 std::map
<reg_t
,uint64_t> pc_histogram
;
296 static const size_t OPCODE_CACHE_SIZE
= 8191;
297 insn_desc_t opcode_cache
[OPCODE_CACHE_SIZE
];
300 void take_interrupt(); // take a trap if any interrupts are pending
301 void take_trap(trap_t
& t
, reg_t epc
); // take an exception
302 void disasm(insn_t insn
); // disassemble and print an instruction
305 void enter_debug_mode(uint8_t cause
);
310 friend class extension_t
;
312 void parse_isa_string(const char* isa
);
313 void build_opcode_map();
314 void register_base_instructions();
315 insn_func_t
decode_insn(insn_t insn
);
318 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
320 #define REGISTER_INSN(proc, name, match, mask) \
321 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
322 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
323 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});