1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
11 #include "debug_rom/debug_rom_defines.h"
15 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
29 struct commit_log_reg_t
49 ACTION_DEBUG_EXCEPTION
= MCONTROL_ACTION_DEBUG_EXCEPTION
,
50 ACTION_DEBUG_MODE
= MCONTROL_ACTION_DEBUG_MODE
,
51 ACTION_TRACE_START
= MCONTROL_ACTION_TRACE_START
,
52 ACTION_TRACE_STOP
= MCONTROL_ACTION_TRACE_STOP
,
53 ACTION_TRACE_EMIT
= MCONTROL_ACTION_TRACE_EMIT
58 MATCH_EQUAL
= MCONTROL_MATCH_EQUAL
,
59 MATCH_NAPOT
= MCONTROL_MATCH_NAPOT
,
60 MATCH_GE
= MCONTROL_MATCH_GE
,
61 MATCH_LT
= MCONTROL_MATCH_LT
,
62 MATCH_MASK_LOW
= MCONTROL_MATCH_MASK_LOW
,
63 MATCH_MASK_HIGH
= MCONTROL_MATCH_MASK_HIGH
73 mcontrol_action_t action
;
75 mcontrol_match_t match
;
85 // architectural state of a RISC-V hart
90 static const int num_triggers
= 4;
93 regfile_t
<reg_t
, NXPR
, true> XPR
;
94 regfile_t
<freg_t
, NFPR
, false> FPR
;
96 // control and status registers
97 reg_t prv
; // TODO: Can this be an enum instead?
121 mcontrol_t mcontrol
[num_triggers
];
122 reg_t tdata2
[num_triggers
];
126 bool serialized
; // whether timer CSRs are in a well-defined state
128 // When true, execute a single instruction and then enter debug mode. This
129 // can only be set by executing dret.
136 reg_t load_reservation
;
138 #ifdef RISCV_ENABLE_COMMITLOG
139 commit_log_reg_t log_reg_write
;
140 reg_t last_inst_priv
;
150 } trigger_operation_t
;
152 // Count number of contiguous 1 bits starting from the LSB.
153 static int cto(reg_t val
)
156 while ((val
& 1) == 1)
161 // this class represents one processor in a RISC-V machine.
162 class processor_t
: public abstract_device_t
165 processor_t(const char* isa
, sim_t
* sim
, uint32_t id
, bool halt_on_reset
=false);
168 void set_debug(bool value
);
169 void set_histogram(bool value
);
171 void step(size_t n
); // run for n cycles
172 void set_csr(int which
, reg_t val
);
173 reg_t
get_csr(int which
);
174 mmu_t
* get_mmu() { return mmu
; }
175 state_t
* get_state() { return &state
; }
176 unsigned get_xlen() { return xlen
; }
177 unsigned get_flen() {
178 return supports_extension('Q') ? 128 :
179 supports_extension('D') ? 64 :
180 supports_extension('F') ? 32 : 0;
182 extension_t
* get_extension() { return ext
; }
183 bool supports_extension(unsigned char ext
) {
184 if (ext
>= 'a' && ext
<= 'z') ext
+= 'A' - 'a';
185 return ext
>= 'A' && ext
<= 'Z' && ((isa
>> (ext
- 'A')) & 1);
187 void set_privilege(reg_t
);
188 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
189 void update_histogram(reg_t pc
);
190 const disassembler_t
* get_disassembler() { return disassembler
; }
192 void register_insn(insn_desc_t
);
193 void register_extension(extension_t
*);
195 // MMIO slave interface
196 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
197 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
199 // When true, display disassembly of each instruction that's executed.
201 // When true, take the slow simulation path.
203 bool halted() { return state
.dcsr
.cause
? true : false; }
206 // Return the index of a trigger that matched, or -1.
207 inline int trigger_match(trigger_operation_t operation
, reg_t address
, reg_t data
)
209 if (state
.dcsr
.cause
)
212 bool chain_ok
= true;
214 for (unsigned int i
= 0; i
< state
.num_triggers
; i
++) {
216 chain_ok
|= !state
.mcontrol
[i
].chain
;
220 if ((operation
== OPERATION_EXECUTE
&& !state
.mcontrol
[i
].execute
) ||
221 (operation
== OPERATION_STORE
&& !state
.mcontrol
[i
].store
) ||
222 (operation
== OPERATION_LOAD
&& !state
.mcontrol
[i
].load
) ||
223 (state
.prv
== PRV_M
&& !state
.mcontrol
[i
].m
) ||
224 (state
.prv
== PRV_H
&& !state
.mcontrol
[i
].h
) ||
225 (state
.prv
== PRV_S
&& !state
.mcontrol
[i
].s
) ||
226 (state
.prv
== PRV_U
&& !state
.mcontrol
[i
].u
)) {
231 if (state
.mcontrol
[i
].select
) {
237 // We need this because in 32-bit mode sometimes the PC bits get sign
243 switch (state
.mcontrol
[i
].match
) {
245 if (value
!= state
.tdata2
[i
])
250 reg_t mask
= ~((1 << cto(state
.tdata2
[i
])) - 1);
251 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
256 if (value
< state
.tdata2
[i
])
260 if (value
>= state
.tdata2
[i
])
265 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
266 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
270 case MATCH_MASK_HIGH
:
272 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
273 if (((value
>> (xlen
/2)) & mask
) != (state
.tdata2
[i
] & mask
))
279 if (!state
.mcontrol
[i
].chain
) {
287 void trigger_updated();
291 mmu_t
* mmu
; // main memory is always accessed via the mmu
293 disassembler_t
* disassembler
;
300 std::string isa_string
;
301 bool histogram_enabled
;
304 std::vector
<insn_desc_t
> instructions
;
305 std::map
<reg_t
,uint64_t> pc_histogram
;
307 static const size_t OPCODE_CACHE_SIZE
= 8191;
308 insn_desc_t opcode_cache
[OPCODE_CACHE_SIZE
];
310 void take_pending_interrupt() { take_interrupt(state
.mip
& state
.mie
); }
311 void take_interrupt(reg_t mask
); // take first enabled interrupt in mask
312 void take_trap(trap_t
& t
, reg_t epc
); // take an exception
313 void disasm(insn_t insn
); // disassemble and print an instruction
316 void enter_debug_mode(uint8_t cause
);
320 friend class clint_t
;
321 friend class extension_t
;
323 void parse_isa_string(const char* isa
);
324 void build_opcode_map();
325 void register_base_instructions();
326 insn_func_t
decode_insn(insn_t insn
);
328 // Track repeated executions for processor_t::disasm()
329 uint64_t last_pc
, last_bits
, executions
;
332 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
334 #define REGISTER_INSN(proc, name, match, mask) \
335 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
336 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
337 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});