riscv/processor.h

   1 // See LICENSE for license details.
   2 #ifndef _RISCV_PROCESSOR_H
   3 #define _RISCV_PROCESSOR_H
   4
   5 #include "decode.h"
   6 #include "config.h"
   7 #include "devices.h"
   8 #include <string>
   9 #include <vector>
  10 #include <map>
  11
  12 class processor_t;
  13 class mmu_t;
  14 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
  15 class sim_t;
  16 class trap_t;
  17 class extension_t;
  18 class disassembler_t;
  19
  20 struct insn_desc_t
  21 {
  22   insn_bits_t match;
  23   insn_bits_t mask;
  24   insn_func_t rv32;
  25   insn_func_t rv64;
  26 };
  27
  28 struct commit_log_reg_t
  29 {
  30   reg_t addr;
  31   reg_t data;
  32 };
  33
  34 typedef struct
  35 {
  36   uint8_t prv;
  37   bool step;
  38   bool ebreakm;
  39   bool ebreakh;
  40   bool ebreaks;
  41   bool ebreaku;
  42   bool halt;
  43   uint8_t cause;
  44 } dcsr_t;
  45
  46 typedef enum
  47 {
  48   ACTION_NONE = MCONTROL_ACTION_NONE,
  49   ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
  50   ACTION_DEBUG_MODE = MCONTROL_ACTION_DEBUG_MODE,
  51   ACTION_TRACE_START = MCONTROL_ACTION_TRACE_START,
  52   ACTION_TRACE_STOP = MCONTROL_ACTION_TRACE_STOP,
  53   ACTION_TRACE_EMIT = MCONTROL_ACTION_TRACE_EMIT
  54 } mcontrol_action_t;
  55
  56 typedef enum
  57 {
  58   MATCH_EQUAL = MCONTROL_MATCH_EQUAL,
  59   MATCH_NAPOT = MCONTROL_MATCH_NAPOT,
  60   MATCH_GE = MCONTROL_MATCH_GE,
  61   MATCH_LT = MCONTROL_MATCH_LT,
  62   MATCH_MASK_LOW = MCONTROL_MATCH_MASK_LOW,
  63   MATCH_MASK_HIGH = MCONTROL_MATCH_MASK_HIGH
  64 } mcontrol_match_t;
  65
  66 typedef struct
  67 {
  68   uint8_t type;
  69   uint8_t maskmax;
  70   bool select;
  71   mcontrol_action_t action;
  72   bool chain;
  73   mcontrol_match_t match;
  74   bool m;
  75   bool h;
  76   bool s;
  77   bool u;
  78   bool execute;
  79   bool store;
  80   bool load;
  81 } mcontrol_t;
  82
  83 // architectural state of a RISC-V hart
  84 struct state_t
  85 {
  86   void reset();
  87
  88   static const int num_triggers = 4;
  89
  90   reg_t pc;
  91   regfile_t<reg_t, NXPR, true> XPR;
  92   regfile_t<freg_t, NFPR, false> FPR;
  93
  94   // control and status registers
  95   reg_t prv;    // TODO: Can this be an enum instead?
  96   reg_t mstatus;
  97   reg_t mepc;
  98   reg_t mbadaddr;
  99   reg_t mscratch;
 100   reg_t mtvec;
 101   reg_t mcause;
 102   reg_t minstret;
 103   reg_t mie;
 104   reg_t mip;
 105   reg_t medeleg;
 106   reg_t mideleg;
 107   reg_t mucounteren;
 108   reg_t mscounteren;
 109   reg_t sepc;
 110   reg_t sbadaddr;
 111   reg_t sscratch;
 112   reg_t stvec;
 113   reg_t sptbr;
 114   reg_t scause;
 115   reg_t dpc;
 116   reg_t dscratch;
 117   dcsr_t dcsr;
 118   reg_t tselect;
 119   mcontrol_t mcontrol[num_triggers];
 120   reg_t tdata1[num_triggers];
 121
 122   uint32_t fflags;
 123   uint32_t frm;
 124   bool serialized; // whether timer CSRs are in a well-defined state
 125
 126   // When true, execute a single instruction and then enter debug mode.  This
 127   // can only be set by executing dret.
 128   enum {
 129       STEP_NONE,
 130       STEP_STEPPING,
 131       STEP_STEPPED
 132   } single_step;
 133
 134   reg_t load_reservation;
 135
 136 #ifdef RISCV_ENABLE_COMMITLOG
 137   commit_log_reg_t log_reg_write;
 138   reg_t last_inst_priv;
 139 #endif
 140 };
 141
 142 typedef enum {
 143   OPERATION_EXECUTE,
 144   OPERATION_STORE,
 145   OPERATION_LOAD,
 146 } trigger_operation_t;
 147
 148 // Count number of contiguous 1 bits starting from the LSB.
 149 static int cto(reg_t val)
 150 {
 151   int res = 0;
 152   while ((val & 1) == 1)
 153     val >>= 1, res++;
 154   return res;
 155 }
 156
 157 // this class represents one processor in a RISC-V machine.
 158 class processor_t : public abstract_device_t
 159 {
 160 public:
 161   processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset=false);
 162   ~processor_t();
 163
 164   void set_debug(bool value);
 165   void set_histogram(bool value);
 166   void reset();
 167   void step(size_t n); // run for n cycles
 168   void set_csr(int which, reg_t val);
 169   void raise_interrupt(reg_t which);
 170   reg_t get_csr(int which);
 171   mmu_t* get_mmu() { return mmu; }
 172   state_t* get_state() { return &state; }
 173   extension_t* get_extension() { return ext; }
 174   bool supports_extension(unsigned char ext) {
 175     if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
 176     return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
 177   }
 178   void set_privilege(reg_t);
 179   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
 180   void update_histogram(reg_t pc);
 181   const disassembler_t* get_disassembler() { return disassembler; }
 182
 183   void register_insn(insn_desc_t);
 184   void register_extension(extension_t*);
 185
 186   // MMIO slave interface
 187   bool load(reg_t addr, size_t len, uint8_t* bytes);
 188   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 189
 190   // When true, display disassembly of each instruction that's executed.
 191   bool debug;
 192   void update_slow_path();
 193
 194   // Return the index of a trigger that matched, or -1.
 195   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
 196   {
 197     if (state.dcsr.cause)
 198       return -1;
 199
 200     bool chain_ok = false;
 201
 202     for (unsigned int i = 0; i < state.num_triggers; i++) {
 203       if (state.mcontrol[i].action == ACTION_NONE ||
 204           (operation == OPERATION_EXECUTE && !state.mcontrol[i].execute) ||
 205           (operation == OPERATION_STORE && !state.mcontrol[i].store) ||
 206           (operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
 207           (state.prv == PRV_M && !state.mcontrol[i].m) ||
 208           (state.prv == PRV_H && !state.mcontrol[i].h) ||
 209           (state.prv == PRV_S && !state.mcontrol[i].s) ||
 210           (state.prv == PRV_U && !state.mcontrol[i].u)) {
 211         goto next;
 212       }
 213
 214       reg_t value;
 215       if (state.mcontrol[i].select) {
 216         value = data;
 217       } else {
 218         value = address;
 219       }
 220
 221       // We need this because in 32-bit mode sometimes the PC bits get sign
 222       // extended.
 223       if (xlen == 32) {
 224         value &= 0xffffffff;
 225       }
 226
 227       switch (state.mcontrol[i].match) {
 228         case MATCH_EQUAL:
 229           if (value != state.tdata1[i])
 230             goto next;
 231           break;
 232         case MATCH_NAPOT:
 233           {
 234             reg_t mask = ~((1 << cto(state.tdata1[i])) - 1);
 235             if ((value & mask) != (state.tdata1[i] & mask))
 236               goto next;
 237           }
 238           break;
 239         case MATCH_GE:
 240           if (value < state.tdata1[i])
 241             goto next;
 242           break;
 243         case MATCH_LT:
 244           if (value >= state.tdata1[i])
 245             goto next;
 246           break;
 247         case MATCH_MASK_LOW:
 248           {
 249             reg_t mask = state.tdata1[i] >> (xlen/2);
 250             if ((value & mask) != (state.tdata1[i] & mask))
 251               goto next;
 252           }
 253           break;
 254         case MATCH_MASK_HIGH:
 255           {
 256             reg_t mask = state.tdata1[i] >> (xlen/2);
 257             if (((value >> (xlen/2)) & mask) != (state.tdata1[i] & mask))
 258               goto next;
 259           }
 260           break;
 261       }
 262
 263       if (state.mcontrol[i].chain && !chain_ok) {
 264         goto next;
 265       }
 266
 267       // We got here, so this trigger matches. But if the next trigger has
 268       // chain set, then we can't perform the action.
 269       if (i+1 < state.num_triggers && state.mcontrol[i+1].chain) {
 270         chain_ok = true;
 271         continue;
 272       } else {
 273         return i;
 274       }
 275
 276 next:
 277       chain_ok = false;
 278     }
 279     return -1;
 280   }
 281
 282   void trigger_updated();
 283
 284 private:
 285   sim_t* sim;
 286   mmu_t* mmu; // main memory is always accessed via the mmu
 287   extension_t* ext;
 288   disassembler_t* disassembler;
 289   state_t state;
 290   uint32_t id;
 291   unsigned max_xlen;
 292   unsigned xlen;
 293   reg_t isa;
 294   std::string isa_string;
 295   bool histogram_enabled;
 296   bool halt_on_reset;
 297   // When true, take the slow simulation path.
 298   bool slow_path;
 299
 300   std::vector<insn_desc_t> instructions;
 301   std::map<reg_t,uint64_t> pc_histogram;
 302
 303   static const size_t OPCODE_CACHE_SIZE = 8191;
 304   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 305
 306   void check_timer();
 307   void take_interrupt(); // take a trap if any interrupts are pending
 308   void take_trap(trap_t& t, reg_t epc); // take an exception
 309   void disasm(insn_t insn); // disassemble and print an instruction
 310   int paddr_bits();
 311
 312   void enter_debug_mode(uint8_t cause);
 313
 314   friend class sim_t;
 315   friend class mmu_t;
 316   friend class rtc_t;
 317   friend class extension_t;
 318
 319   void parse_isa_string(const char* isa);
 320   void build_opcode_map();
 321   void register_base_instructions();
 322   insn_func_t decode_insn(insn_t insn);
 323 };
 324
 325 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);
 326
 327 #define REGISTER_INSN(proc, name, match, mask) \
 328   extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
 329   extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
 330   proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});
 331
 332 #endif