1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
13 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
27 struct commit_log_reg_t
33 // architectural state of a RISC-V hart
39 regfile_t
<reg_t
, NXPR
, true> XPR
;
40 regfile_t
<freg_t
, NFPR
, false> FPR
;
42 // control and status registers
62 reg_t load_reservation
;
64 #ifdef RISCV_ENABLE_COMMITLOG
65 commit_log_reg_t log_reg_write
;
69 // this class represents one processor in a RISC-V machine.
73 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
);
76 void set_debug(bool value
);
77 void set_histogram(bool value
);
78 void reset(bool value
);
79 void step(size_t n
); // run for n cycles
80 void deliver_ipi(); // register an interprocessor interrupt
81 bool running() { return run
; }
82 void set_csr(int which
, reg_t val
);
83 void raise_interrupt(reg_t which
);
84 reg_t
get_csr(int which
);
85 mmu_t
* get_mmu() { return mmu
; }
86 state_t
* get_state() { return &state
; }
87 extension_t
* get_extension() { return ext
; }
88 void push_privilege_stack();
89 void pop_privilege_stack();
90 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
91 void update_histogram(size_t pc
);
93 void register_insn(insn_desc_t
);
94 void register_extension(extension_t
*);
98 mmu_t
* mmu
; // main memory is always accessed via the mmu
100 disassembler_t
* disassembler
;
106 bool histogram_enabled
;
109 std::vector
<insn_desc_t
> instructions
;
110 std::vector
<insn_desc_t
*> opcode_map
;
111 std::vector
<insn_desc_t
> opcode_store
;
112 std::map
<size_t,size_t> pc_histogram
;
114 void take_interrupt(); // take a trap if any interrupts are pending
115 void serialize(); // collapse into defined architectural state
116 reg_t
take_trap(trap_t
& t
, reg_t epc
); // take an exception
117 void disasm(insn_t insn
); // disassemble and print an instruction
121 friend class extension_t
;
123 void build_opcode_map();
124 insn_func_t
decode_insn(insn_t insn
);
127 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
129 #define REGISTER_INSN(proc, name, match, mask) \
130 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
131 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
132 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});