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[opcodes] generate latex and verilog correctly
[riscv-isa-sim.git]
/
riscv
/
riscv.mk.in
1
riscv_subproject_deps
=
\
2
softfloat_riscv \
3
softfloat \
4
5
riscv_hdrs
=
\
6
applink.h \
7
common.h \
8
decode.h \
9
execute.h \
10
mmu.h \
11
processor.h \
12
sim.h \
13
trap.h \
14
insns
/*
.h \
15
16
riscv_srcs
=
\
17
applink.
cc
\
18
processor.
cc
\
19
sim.
cc
\
20
trap.
cc
\
21
22
riscv_test_srcs
=
23
24
riscv_install_prog_srcs
=
\
25
riscv-isa-run.
cc
\