1 // See LICENSE for license details.
14 volatile bool ctrlc_pressed
= false;
15 static void handle_signal(int sig
)
20 signal(sig
, &handle_signal
);
23 sim_t::sim_t(const char* isa
, size_t nprocs
, size_t mem_mb
, bool halted
,
24 const std::vector
<std::string
>& args
)
25 : htif_t(args
), procs(std::max(nprocs
, size_t(1))),
26 current_step(0), current_proc(0), debug(false), gdbserver(NULL
)
28 signal(SIGINT
, &handle_signal
);
29 // allocate target machine's memory, shrinking it as necessary
30 // until the allocation succeeds
31 size_t memsz0
= (size_t)mem_mb
<< 20;
32 size_t quantum
= 1L << 20;
34 memsz0
= (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
37 while ((mem
= (char*)calloc(1, memsz
)) == NULL
)
38 memsz
= (size_t)(memsz
*0.9)/quantum
*quantum
;
41 fprintf(stderr
, "warning: only got %lu bytes of target mem (wanted %lu)\n",
42 (unsigned long)memsz
, (unsigned long)memsz0
);
44 bus
.add_device(DEBUG_START
, &debug_module
);
46 debug_mmu
= new mmu_t(this, NULL
);
48 for (size_t i
= 0; i
< procs
.size(); i
++) {
49 procs
[i
] = new processor_t(isa
, this, i
, halted
);
52 rtc
.reset(new rtc_t(procs
));
58 for (size_t i
= 0; i
< procs
.size(); i
++)
64 void sim_thread_main(void* arg
)
66 ((sim_t
*)arg
)->main();
72 set_procs_debug(true);
76 if (debug
|| ctrlc_pressed
)
88 host
= context_t::current();
89 target
.init(sim_thread_main
, this);
93 void sim_t::step(size_t n
)
95 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
97 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
98 procs
[current_proc
]->step(steps
);
100 current_step
+= steps
;
101 if (current_step
== INTERLEAVE
)
104 procs
[current_proc
]->yield_load_reservation();
105 if (++current_proc
== procs
.size()) {
107 rtc
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
115 void sim_t::set_debug(bool value
)
120 void sim_t::set_log(bool value
)
125 void sim_t::set_histogram(bool value
)
127 histogram_enabled
= value
;
128 for (size_t i
= 0; i
< procs
.size(); i
++) {
129 procs
[i
]->set_histogram(histogram_enabled
);
133 void sim_t::set_procs_debug(bool value
)
135 for (size_t i
=0; i
< procs
.size(); i
++)
136 procs
[i
]->set_debug(value
);
139 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
141 if (addr
+ len
< addr
)
143 return bus
.load(addr
, len
, bytes
);
146 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
148 if (addr
+ len
< addr
)
150 return bus
.store(addr
, len
, bytes
);
153 void sim_t::make_config_string()
155 reg_t rtc_addr
= EXT_IO_BASE
;
156 bus
.add_device(rtc_addr
, rtc
.get());
158 const int align
= 0x1000;
159 reg_t cpu_addr
= rtc_addr
+ ((rtc
->size() - 1) / align
+ 1) * align
;
160 reg_t cpu_size
= align
;
162 uint32_t reset_vec
[8] = {
163 0x297 + DRAM_BASE
- DEFAULT_RSTVEC
, // reset vector
164 0x00028067, // jump straight to DRAM_BASE
165 0x00000000, // reserved
166 0, // config string pointer
167 0, 0, 0, 0 // trap vector
169 reset_vec
[3] = DEFAULT_RSTVEC
+ sizeof(reset_vec
); // config string pointer
171 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
180 " addr 0x" << rtc_addr
<< ";\n"
184 " addr 0x" << DRAM_BASE
<< ";\n"
185 " size 0x" << memsz
<< ";\n"
189 for (size_t i
= 0; i
< procs
.size(); i
++) {
192 " " << "0 {\n" << // hart 0 on core i
193 " isa " << procs
[i
]->isa_string
<< ";\n"
194 " timecmp 0x" << (rtc_addr
+ 8*(1+i
)) << ";\n"
195 " ipi 0x" << cpu_addr
<< ";\n"
198 bus
.add_device(cpu_addr
, procs
[i
]);
199 cpu_addr
+= cpu_size
;
203 config_string
= s
.str();
204 rom
.insert(rom
.end(), config_string
.begin(), config_string
.end());
205 rom
.resize((rom
.size() / align
+ 1) * align
);
207 boot_rom
.reset(new rom_device_t(rom
));
208 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());
218 void sim_t::read_chunk(addr_t taddr
, size_t len
, void* dst
)
221 auto data
= debug_mmu
->load_uint64(taddr
);
222 memcpy(dst
, &data
, sizeof data
);
225 void sim_t::write_chunk(addr_t taddr
, size_t len
, const void* src
)
229 memcpy(&data
, src
, sizeof data
);
230 debug_mmu
->store_uint64(taddr
, data
);