1 // See LICENSE for license details.
5 #include "remote_bitbang.h"
15 #include <sys/types.h>
17 volatile bool ctrlc_pressed
= false;
18 static void handle_signal(int sig
)
23 signal(sig
, &handle_signal
);
26 sim_t::sim_t(const char* isa
, size_t nprocs
, bool halted
, reg_t start_pc
,
27 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
,
28 const std::vector
<std::string
>& args
)
29 : htif_t(args
), debug_module(this), mems(mems
), procs(std::max(nprocs
, size_t(1))),
31 current_step(0), current_proc(0), debug(false), remote_bitbang(NULL
)
33 signal(SIGINT
, &handle_signal
);
36 bus
.add_device(x
.first
, x
.second
);
38 debug_module
.add_device(&bus
);
40 debug_mmu
= new mmu_t(this, NULL
);
42 for (size_t i
= 0; i
< procs
.size(); i
++) {
43 procs
[i
] = new processor_t(isa
, this, i
, halted
);
46 clint
.reset(new clint_t(procs
));
47 bus
.add_device(CLINT_BASE
, clint
.get());
52 for (size_t i
= 0; i
< procs
.size(); i
++)
57 void sim_thread_main(void* arg
)
59 ((sim_t
*)arg
)->main();
65 set_procs_debug(true);
69 if (debug
|| ctrlc_pressed
)
74 remote_bitbang
->tick();
81 host
= context_t::current();
82 target
.init(sim_thread_main
, this);
86 void sim_t::step(size_t n
)
88 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
90 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
91 procs
[current_proc
]->step(steps
);
93 current_step
+= steps
;
94 if (current_step
== INTERLEAVE
)
97 procs
[current_proc
]->yield_load_reservation();
98 if (++current_proc
== procs
.size()) {
100 clint
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
108 void sim_t::set_debug(bool value
)
113 void sim_t::set_log(bool value
)
118 void sim_t::set_histogram(bool value
)
120 histogram_enabled
= value
;
121 for (size_t i
= 0; i
< procs
.size(); i
++) {
122 procs
[i
]->set_histogram(histogram_enabled
);
126 void sim_t::set_procs_debug(bool value
)
128 for (size_t i
=0; i
< procs
.size(); i
++)
129 procs
[i
]->set_debug(value
);
132 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
134 if (addr
+ len
< addr
)
136 return bus
.load(addr
, len
, bytes
);
139 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
141 if (addr
+ len
< addr
)
143 return bus
.store(addr
, len
, bytes
);
146 static std::string
dts_compile(const std::string
& dts
)
148 // Convert the DTS to DTB
152 if (pipe(dts_pipe
) != 0 || (dts_pid
= fork()) < 0) {
153 std::cerr
<< "Failed to fork dts child: " << strerror(errno
) << std::endl
;
157 // Child process to output dts
160 int step
, len
= dts
.length();
161 const char *buf
= dts
.c_str();
162 for (int done
= 0; done
< len
; done
+= step
) {
163 step
= write(dts_pipe
[1], buf
+done
, len
-done
);
165 std::cerr
<< "Failed to write dts: " << strerror(errno
) << std::endl
;
175 if (pipe(dtb_pipe
) != 0 || (dtb_pid
= fork()) < 0) {
176 std::cerr
<< "Failed to fork dtb child: " << strerror(errno
) << std::endl
;
180 // Child process to output dtb
182 dup2(dts_pipe
[0], 0);
183 dup2(dtb_pipe
[1], 1);
188 execl(DTC
, DTC
, "-O", "dtb", 0);
189 std::cerr
<< "Failed to run " DTC
": " << strerror(errno
) << std::endl
;
198 std::stringstream dtb
;
202 while ((got
= read(dtb_pipe
[0], buf
, sizeof(buf
))) > 0) {
206 std::cerr
<< "Failed to read dtb: " << strerror(errno
) << std::endl
;
213 waitpid(dts_pid
, &status
, 0);
214 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
215 std::cerr
<< "Child dts process failed" << std::endl
;
218 waitpid(dtb_pid
, &status
, 0);
219 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
220 std::cerr
<< "Child dtb process failed" << std::endl
;
227 void sim_t::make_dtb()
229 const int reset_vec_size
= 8;
231 start_pc
= start_pc
== reg_t(-1) ? get_entry_point() : start_pc
;
233 uint32_t reset_vec
[reset_vec_size
] = {
234 0x297, // auipc t0,0x0
235 0x28593 + (reset_vec_size
* 4 << 20), // addi a1, t0, &dtb
236 0xf1402573, // csrr a0, mhartid
237 get_core(0)->xlen
== 32 ?
238 0x0182a283u
: // lw t0,24(t0)
239 0x0182b283u
, // ld t0,24(t0)
242 (uint32_t) (start_pc
& 0xffffffff),
243 (uint32_t) (start_pc
>> 32)
246 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
253 " #address-cells = <2>;\n"
254 " #size-cells = <2>;\n"
255 " compatible = \"ucbbar,spike-bare-dev\";\n"
256 " model = \"ucbbar,spike-bare\";\n"
258 " #address-cells = <1>;\n"
259 " #size-cells = <0>;\n"
260 " timebase-frequency = <" << (CPU_HZ
/INSNS_PER_RTC_TICK
) << ">;\n";
261 for (size_t i
= 0; i
< procs
.size(); i
++) {
262 s
<< " CPU" << i
<< ": cpu@" << i
<< " {\n"
263 " device_type = \"cpu\";\n"
264 " reg = <" << i
<< ">;\n"
265 " status = \"okay\";\n"
266 " compatible = \"riscv\";\n"
267 " riscv,isa = \"" << procs
[i
]->isa_string
<< "\";\n"
268 " mmu-type = \"riscv," << (procs
[i
]->max_xlen
<= 32 ? "sv32" : "sv48") << "\";\n"
269 " clock-frequency = <" << CPU_HZ
<< ">;\n"
270 " CPU" << i
<< "_intc: interrupt-controller {\n"
271 " #interrupt-cells = <1>;\n"
272 " interrupt-controller;\n"
273 " compatible = \"riscv,cpu-intc\";\n"
278 for (auto& m
: mems
) {
280 " memory@" << m
.first
<< " {\n"
281 " device_type = \"memory\";\n"
282 " reg = <0x" << (m
.first
>> 32) << " 0x" << (m
.first
& (uint32_t)-1) <<
283 " 0x" << (m
.second
->size() >> 32) << " 0x" << (m
.second
->size() & (uint32_t)-1) << ">;\n"
287 " #address-cells = <2>;\n"
288 " #size-cells = <2>;\n"
289 " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
291 " clint@" << CLINT_BASE
<< " {\n"
292 " compatible = \"riscv,clint0\";\n"
293 " interrupts-extended = <" << std::dec
;
294 for (size_t i
= 0; i
< procs
.size(); i
++)
295 s
<< "&CPU" << i
<< "_intc 3 &CPU" << i
<< "_intc 7 ";
296 reg_t clintbs
= CLINT_BASE
;
297 reg_t clintsz
= CLINT_SIZE
;
298 s
<< std::hex
<< ">;\n"
299 " reg = <0x" << (clintbs
>> 32) << " 0x" << (clintbs
& (uint32_t)-1) <<
300 " 0x" << (clintsz
>> 32) << " 0x" << (clintsz
& (uint32_t)-1) << ">;\n"
306 std::string dtb
= dts_compile(dts
);
308 rom
.insert(rom
.end(), dtb
.begin(), dtb
.end());
309 const int align
= 0x1000;
310 rom
.resize((rom
.size() + align
- 1) / align
* align
);
312 boot_rom
.reset(new rom_device_t(rom
));
313 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());
316 char* sim_t::addr_to_mem(reg_t addr
) {
317 auto desc
= bus
.find_device(addr
);
318 if (auto mem
= dynamic_cast<mem_t
*>(desc
.second
))
319 if (addr
- desc
.first
< mem
->size())
320 return mem
->contents() + (addr
- desc
.first
);
336 void sim_t::read_chunk(addr_t taddr
, size_t len
, void* dst
)
339 auto data
= debug_mmu
->load_uint64(taddr
);
340 memcpy(dst
, &data
, sizeof data
);
343 void sim_t::write_chunk(addr_t taddr
, size_t len
, const void* src
)
347 memcpy(&data
, src
, sizeof data
);
348 debug_mmu
->store_uint64(taddr
, data
);