1 // See LICENSE for license details.
5 #include "remote_bitbang.h"
15 #include <sys/types.h>
17 volatile bool ctrlc_pressed
= false;
18 static void handle_signal(int sig
)
23 signal(sig
, &handle_signal
);
26 sim_t::sim_t(const char* isa
, size_t nprocs
, bool halted
, reg_t start_pc
,
27 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
,
28 const std::vector
<std::string
>& args
,
29 std::vector
<int> const hartids
, unsigned progsize
,
30 unsigned max_bus_master_bits
, bool require_authentication
)
31 : htif_t(args
), mems(mems
), procs(std::max(nprocs
, size_t(1))),
32 start_pc(start_pc
), current_step(0), current_proc(0), debug(false),
34 debug_module(this, progsize
, max_bus_master_bits
, require_authentication
)
36 signal(SIGINT
, &handle_signal
);
39 bus
.add_device(x
.first
, x
.second
);
41 debug_module
.add_device(&bus
);
43 debug_mmu
= new mmu_t(this, NULL
);
45 if (hartids
.size() == 0) {
46 for (size_t i
= 0; i
< procs
.size(); i
++) {
47 procs
[i
] = new processor_t(isa
, this, i
, halted
);
51 if (hartids
.size() != procs
.size()) {
52 std::cerr
<< "Number of specified hartids doesn't match number of processors" << strerror(errno
) << std::endl
;
55 for (size_t i
= 0; i
< procs
.size(); i
++) {
56 procs
[i
] = new processor_t(isa
, this, hartids
[i
], halted
);
60 clint
.reset(new clint_t(procs
));
61 bus
.add_device(CLINT_BASE
, clint
.get());
66 for (size_t i
= 0; i
< procs
.size(); i
++)
71 void sim_thread_main(void* arg
)
73 ((sim_t
*)arg
)->main();
79 set_procs_debug(true);
83 if (debug
|| ctrlc_pressed
)
88 remote_bitbang
->tick();
95 host
= context_t::current();
96 target
.init(sim_thread_main
, this);
100 void sim_t::step(size_t n
)
102 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
104 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
105 procs
[current_proc
]->step(steps
);
107 current_step
+= steps
;
108 if (current_step
== INTERLEAVE
)
111 procs
[current_proc
]->yield_load_reservation();
112 if (++current_proc
== procs
.size()) {
114 clint
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
122 void sim_t::set_debug(bool value
)
127 void sim_t::set_log(bool value
)
132 void sim_t::set_histogram(bool value
)
134 histogram_enabled
= value
;
135 for (size_t i
= 0; i
< procs
.size(); i
++) {
136 procs
[i
]->set_histogram(histogram_enabled
);
140 void sim_t::set_procs_debug(bool value
)
142 for (size_t i
=0; i
< procs
.size(); i
++)
143 procs
[i
]->set_debug(value
);
146 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
148 if (addr
+ len
< addr
)
150 return bus
.load(addr
, len
, bytes
);
153 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
155 if (addr
+ len
< addr
)
157 return bus
.store(addr
, len
, bytes
);
160 static std::string
dts_compile(const std::string
& dts
)
162 // Convert the DTS to DTB
166 if (pipe(dts_pipe
) != 0 || (dts_pid
= fork()) < 0) {
167 std::cerr
<< "Failed to fork dts child: " << strerror(errno
) << std::endl
;
171 // Child process to output dts
174 int step
, len
= dts
.length();
175 const char *buf
= dts
.c_str();
176 for (int done
= 0; done
< len
; done
+= step
) {
177 step
= write(dts_pipe
[1], buf
+done
, len
-done
);
179 std::cerr
<< "Failed to write dts: " << strerror(errno
) << std::endl
;
189 if (pipe(dtb_pipe
) != 0 || (dtb_pid
= fork()) < 0) {
190 std::cerr
<< "Failed to fork dtb child: " << strerror(errno
) << std::endl
;
194 // Child process to output dtb
196 dup2(dts_pipe
[0], 0);
197 dup2(dtb_pipe
[1], 1);
202 execl(DTC
, DTC
, "-O", "dtb", 0);
203 std::cerr
<< "Failed to run " DTC
": " << strerror(errno
) << std::endl
;
212 std::stringstream dtb
;
216 while ((got
= read(dtb_pipe
[0], buf
, sizeof(buf
))) > 0) {
220 std::cerr
<< "Failed to read dtb: " << strerror(errno
) << std::endl
;
227 waitpid(dts_pid
, &status
, 0);
228 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
229 std::cerr
<< "Child dts process failed" << std::endl
;
232 waitpid(dtb_pid
, &status
, 0);
233 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
234 std::cerr
<< "Child dtb process failed" << std::endl
;
241 void sim_t::make_dtb()
243 const int reset_vec_size
= 8;
245 start_pc
= start_pc
== reg_t(-1) ? get_entry_point() : start_pc
;
247 uint32_t reset_vec
[reset_vec_size
] = {
248 0x297, // auipc t0,0x0
249 0x28593 + (reset_vec_size
* 4 << 20), // addi a1, t0, &dtb
250 0xf1402573, // csrr a0, mhartid
251 get_core(0)->get_xlen() == 32 ?
252 0x0182a283u
: // lw t0,24(t0)
253 0x0182b283u
, // ld t0,24(t0)
256 (uint32_t) (start_pc
& 0xffffffff),
257 (uint32_t) (start_pc
>> 32)
260 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
267 " #address-cells = <2>;\n"
268 " #size-cells = <2>;\n"
269 " compatible = \"ucbbar,spike-bare-dev\";\n"
270 " model = \"ucbbar,spike-bare\";\n"
272 " #address-cells = <1>;\n"
273 " #size-cells = <0>;\n"
274 " timebase-frequency = <" << (CPU_HZ
/INSNS_PER_RTC_TICK
) << ">;\n";
275 for (size_t i
= 0; i
< procs
.size(); i
++) {
276 s
<< " CPU" << i
<< ": cpu@" << i
<< " {\n"
277 " device_type = \"cpu\";\n"
278 " reg = <" << i
<< ">;\n"
279 " status = \"okay\";\n"
280 " compatible = \"riscv\";\n"
281 " riscv,isa = \"" << procs
[i
]->get_isa_string() << "\";\n"
282 " mmu-type = \"riscv," << (procs
[i
]->get_max_xlen() <= 32 ? "sv32" : "sv48") << "\";\n"
283 " clock-frequency = <" << CPU_HZ
<< ">;\n"
284 " CPU" << i
<< "_intc: interrupt-controller {\n"
285 " #interrupt-cells = <1>;\n"
286 " interrupt-controller;\n"
287 " compatible = \"riscv,cpu-intc\";\n"
292 for (auto& m
: mems
) {
294 " memory@" << m
.first
<< " {\n"
295 " device_type = \"memory\";\n"
296 " reg = <0x" << (m
.first
>> 32) << " 0x" << (m
.first
& (uint32_t)-1) <<
297 " 0x" << (m
.second
->size() >> 32) << " 0x" << (m
.second
->size() & (uint32_t)-1) << ">;\n"
301 " #address-cells = <2>;\n"
302 " #size-cells = <2>;\n"
303 " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
305 " clint@" << CLINT_BASE
<< " {\n"
306 " compatible = \"riscv,clint0\";\n"
307 " interrupts-extended = <" << std::dec
;
308 for (size_t i
= 0; i
< procs
.size(); i
++)
309 s
<< "&CPU" << i
<< "_intc 3 &CPU" << i
<< "_intc 7 ";
310 reg_t clintbs
= CLINT_BASE
;
311 reg_t clintsz
= CLINT_SIZE
;
312 s
<< std::hex
<< ">;\n"
313 " reg = <0x" << (clintbs
>> 32) << " 0x" << (clintbs
& (uint32_t)-1) <<
314 " 0x" << (clintsz
>> 32) << " 0x" << (clintsz
& (uint32_t)-1) << ">;\n"
318 " compatible = \"ucb,htif0\";\n"
323 std::string dtb
= dts_compile(dts
);
325 rom
.insert(rom
.end(), dtb
.begin(), dtb
.end());
326 const int align
= 0x1000;
327 rom
.resize((rom
.size() + align
- 1) / align
* align
);
329 boot_rom
.reset(new rom_device_t(rom
));
330 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());
333 char* sim_t::addr_to_mem(reg_t addr
) {
334 auto desc
= bus
.find_device(addr
);
335 if (auto mem
= dynamic_cast<mem_t
*>(desc
.second
))
336 if (addr
- desc
.first
< mem
->size())
337 return mem
->contents() + (addr
- desc
.first
);
353 void sim_t::read_chunk(addr_t taddr
, size_t len
, void* dst
)
356 auto data
= debug_mmu
->load_uint64(taddr
);
357 memcpy(dst
, &data
, sizeof data
);
360 void sim_t::write_chunk(addr_t taddr
, size_t len
, const void* src
)
364 memcpy(&data
, src
, sizeof data
);
365 debug_mmu
->store_uint64(taddr
, data
);