1 // See LICENSE for license details.
15 #include <sys/types.h>
17 volatile bool ctrlc_pressed
= false;
18 static void handle_signal(int sig
)
23 signal(sig
, &handle_signal
);
26 sim_t::sim_t(const char* isa
, size_t nprocs
, bool halted
,
27 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
,
28 const std::vector
<std::string
>& args
)
29 : htif_t(args
), mems(mems
), procs(std::max(nprocs
, size_t(1))),
30 current_step(0), current_proc(0), debug(false), gdbserver(NULL
)
32 signal(SIGINT
, &handle_signal
);
35 bus
.add_device(x
.first
, x
.second
);
37 bus
.add_device(DEBUG_START
, &debug_module
);
39 debug_mmu
= new mmu_t(this, NULL
);
41 for (size_t i
= 0; i
< procs
.size(); i
++) {
42 procs
[i
] = new processor_t(isa
, this, i
, halted
);
45 clint
.reset(new clint_t(procs
));
46 bus
.add_device(CLINT_BASE
, clint
.get());
53 for (size_t i
= 0; i
< procs
.size(); i
++)
58 void sim_thread_main(void* arg
)
60 ((sim_t
*)arg
)->main();
66 set_procs_debug(true);
70 if (debug
|| ctrlc_pressed
)
82 host
= context_t::current();
83 target
.init(sim_thread_main
, this);
87 void sim_t::step(size_t n
)
89 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
91 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
92 procs
[current_proc
]->step(steps
);
94 current_step
+= steps
;
95 if (current_step
== INTERLEAVE
)
98 procs
[current_proc
]->yield_load_reservation();
99 if (++current_proc
== procs
.size()) {
101 clint
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
109 void sim_t::set_debug(bool value
)
114 void sim_t::set_log(bool value
)
119 void sim_t::set_histogram(bool value
)
121 histogram_enabled
= value
;
122 for (size_t i
= 0; i
< procs
.size(); i
++) {
123 procs
[i
]->set_histogram(histogram_enabled
);
127 void sim_t::set_procs_debug(bool value
)
129 for (size_t i
=0; i
< procs
.size(); i
++)
130 procs
[i
]->set_debug(value
);
133 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
135 if (addr
+ len
< addr
)
137 return bus
.load(addr
, len
, bytes
);
140 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
142 if (addr
+ len
< addr
)
144 return bus
.store(addr
, len
, bytes
);
147 static std::string
dts_compile(const std::string
& dts
)
149 // Convert the DTS to DTB
153 if (pipe(dts_pipe
) != 0 || (dts_pid
= fork()) < 0) {
154 std::cerr
<< "Failed to fork dts child: " << strerror(errno
) << std::endl
;
158 // Child process to output dts
161 int step
, len
= dts
.length();
162 const char *buf
= dts
.c_str();
163 for (int done
= 0; done
< len
; done
+= step
) {
164 step
= write(dts_pipe
[1], buf
+done
, len
-done
);
166 std::cerr
<< "Failed to write dts: " << strerror(errno
) << std::endl
;
176 if (pipe(dtb_pipe
) != 0 || (dtb_pid
= fork()) < 0) {
177 std::cerr
<< "Failed to fork dtb child: " << strerror(errno
) << std::endl
;
181 // Child process to output dtb
183 dup2(dts_pipe
[0], 0);
184 dup2(dtb_pipe
[1], 1);
189 execl(DTC
, DTC
, "-O", "dtb", 0);
190 std::cerr
<< "Failed to run " DTC
": " << strerror(errno
) << std::endl
;
199 std::stringstream dtb
;
203 while ((got
= read(dtb_pipe
[0], buf
, sizeof(buf
))) > 0) {
207 std::cerr
<< "Failed to read dtb: " << strerror(errno
) << std::endl
;
214 waitpid(dts_pid
, &status
, 0);
215 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
216 std::cerr
<< "Child dts process failed" << std::endl
;
219 waitpid(dtb_pid
, &status
, 0);
220 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
221 std::cerr
<< "Child dtb process failed" << std::endl
;
228 void sim_t::make_dtb()
230 uint32_t reset_vec
[] = {
231 0x297 + DRAM_BASE
- DEFAULT_RSTVEC
, // auipc t0, DRAM_BASE
232 0x597, // auipc a1, 0
233 0x58593, // addi a1, a1, 0
234 0xf1402573, // csrr a0,mhartid
235 0x00028067 // jalr zero, t0, 0 (jump straight to DRAM_BASE)
237 reset_vec
[2] += (sizeof(reset_vec
) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
239 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
246 " #address-cells = <2>;\n"
247 " #size-cells = <2>;\n"
248 " compatible = \"ucbbar,spike-bare-dev\";\n"
249 " model = \"ucbbar,spike-bare\";\n"
251 " #address-cells = <1>;\n"
252 " #size-cells = <0>;\n"
253 " timebase-frequency = <" << (CPU_HZ
/INSNS_PER_RTC_TICK
) << ">;\n";
254 for (size_t i
= 0; i
< procs
.size(); i
++) {
255 s
<< " CPU" << i
<< ": cpu@" << i
<< " {\n"
256 " device_type = \"cpu\";\n"
257 " reg = <" << i
<< ">;\n"
258 " status = \"okay\";\n"
259 " compatible = \"riscv\";\n"
260 " riscv,isa = \"" << procs
[i
]->isa_string
<< "\";\n"
261 " mmu-type = \"riscv," << (procs
[i
]->max_xlen
<= 32 ? "sv32" : "sv48") << "\";\n"
262 " clock-frequency = <" << CPU_HZ
<< ">;\n"
263 " CPU" << i
<< "_intc: interrupt-controller {\n"
264 " #interrupt-cells = <1>;\n"
265 " interrupt-controller;\n"
266 " compatible = \"riscv,cpu-intc\";\n"
271 for (auto& m
: mems
) {
273 " memory@" << m
.first
<< " {\n"
274 " device_type = \"memory\";\n"
275 " reg = <0x" << (m
.first
>> 32) << " 0x" << (m
.first
& (uint32_t)-1) <<
276 " 0x" << (m
.second
->size() >> 32) << " 0x" << (m
.second
->size() & (uint32_t)-1) << ">;\n"
280 " #address-cells = <2>;\n"
281 " #size-cells = <2>;\n"
282 " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
284 " clint@" << CLINT_BASE
<< " {\n"
285 " compatible = \"riscv,clint0\";\n"
286 " interrupts-extended = <" << std::dec
;
287 for (size_t i
= 0; i
< procs
.size(); i
++)
288 s
<< "&CPU" << i
<< "_intc 3 &CPU" << i
<< "_intc 7 ";
289 reg_t clintbs
= CLINT_BASE
;
290 reg_t clintsz
= CLINT_SIZE
;
291 s
<< std::hex
<< ">;\n"
292 " reg = <0x" << (clintbs
>> 32) << " 0x" << (clintbs
& (uint32_t)-1) <<
293 " 0x" << (clintsz
>> 32) << " 0x" << (clintsz
& (uint32_t)-1) << ">;\n"
299 std::string dtb
= dts_compile(dts
);
301 rom
.insert(rom
.end(), dtb
.begin(), dtb
.end());
302 const int align
= 0x1000;
303 rom
.resize((rom
.size() + align
- 1) / align
* align
);
305 boot_rom
.reset(new rom_device_t(rom
));
306 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());
309 char* sim_t::addr_to_mem(reg_t addr
) {
310 auto desc
= bus
.find_device(addr
);
311 if (auto mem
= dynamic_cast<mem_t
*>(desc
.device
))
312 return mem
->contents() + (addr
- desc
.base
);
323 void sim_t::read_chunk(addr_t taddr
, size_t len
, void* dst
)
326 auto data
= debug_mmu
->load_uint64(taddr
);
327 memcpy(dst
, &data
, sizeof data
);
330 void sim_t::write_chunk(addr_t taddr
, size_t len
, const void* src
)
334 memcpy(&data
, src
, sizeof data
);
335 debug_mmu
->store_uint64(taddr
, data
);