1 // See LICENSE for license details.
8 #include "debug_module.h"
9 #include <fesvr/htif.h>
10 #include <fesvr/context.h>
16 class remote_bitbang_t
;
18 // this is the interface to the simulator used by the processors and memory
22 // should return NULL for MMIO addresses
23 virtual char* addr_to_mem(reg_t addr
) = 0;
24 // used for MMIO addresses
25 virtual bool mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
) = 0;
26 virtual bool mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
) = 0;
27 // Callback for processors to let the simulation know they were reset.
28 virtual void proc_reset(unsigned id
) = 0;
31 // this class encapsulates the processors and memory in a RISC-V machine.
32 class sim_t
: public htif_t
, public simif_t
35 sim_t(const char* isa
, size_t _nprocs
, bool halted
, reg_t start_pc
,
36 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
,
37 const std::vector
<std::string
>& args
, const std::vector
<int> hartids
,
38 unsigned progsize
, unsigned max_bus_master_bits
, bool require_authentication
);
41 // run the simulation to completion
43 void set_debug(bool value
);
44 void set_log(bool value
);
45 void set_histogram(bool value
);
46 void set_procs_debug(bool value
);
47 void set_remote_bitbang(remote_bitbang_t
* remote_bitbang
) {
48 this->remote_bitbang
= remote_bitbang
;
50 const char* get_dts() { if (dts
.empty()) reset(); return dts
.c_str(); }
51 processor_t
* get_core(size_t i
) { return procs
.at(i
); }
52 unsigned nprocs() const { return procs
.size(); }
54 // Callback for processors to let the simulation know they were reset.
55 void proc_reset(unsigned id
);
58 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
;
59 mmu_t
* debug_mmu
; // debug port into main memory
60 std::vector
<processor_t
*> procs
;
63 std::unique_ptr
<rom_device_t
> boot_rom
;
64 std::unique_ptr
<clint_t
> clint
;
67 processor_t
* get_core(const std::string
& i
);
68 void step(size_t n
); // step through simulation
69 static const size_t INTERLEAVE
= 5000;
70 static const size_t INSNS_PER_RTC_TICK
= 100; // 10 MHz clock for 1 BIPS core
71 static const size_t CPU_HZ
= 1000000000; // 1GHz CPU
76 bool histogram_enabled
; // provide a histogram of PCs
77 remote_bitbang_t
* remote_bitbang
;
79 // memory-mapped I/O routines
80 char* addr_to_mem(reg_t addr
);
81 bool mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
);
82 bool mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
);
85 // presents a prompt for introspection into the simulation
88 // functions that help implement interactive()
89 void interactive_help(const std::string
& cmd
, const std::vector
<std::string
>& args
);
90 void interactive_quit(const std::string
& cmd
, const std::vector
<std::string
>& args
);
91 void interactive_run(const std::string
& cmd
, const std::vector
<std::string
>& args
, bool noisy
);
92 void interactive_run_noisy(const std::string
& cmd
, const std::vector
<std::string
>& args
);
93 void interactive_run_silent(const std::string
& cmd
, const std::vector
<std::string
>& args
);
94 void interactive_reg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
95 void interactive_freg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
96 void interactive_fregs(const std::string
& cmd
, const std::vector
<std::string
>& args
);
97 void interactive_fregd(const std::string
& cmd
, const std::vector
<std::string
>& args
);
98 void interactive_pc(const std::string
& cmd
, const std::vector
<std::string
>& args
);
99 void interactive_mem(const std::string
& cmd
, const std::vector
<std::string
>& args
);
100 void interactive_str(const std::string
& cmd
, const std::vector
<std::string
>& args
);
101 void interactive_until(const std::string
& cmd
, const std::vector
<std::string
>& args
);
102 reg_t
get_reg(const std::vector
<std::string
>& args
);
103 freg_t
get_freg(const std::vector
<std::string
>& args
);
104 reg_t
get_mem(const std::vector
<std::string
>& args
);
105 reg_t
get_pc(const std::vector
<std::string
>& args
);
107 friend class processor_t
;
109 friend class debug_module_t
;
112 friend void sim_thread_main(void*);
119 void read_chunk(addr_t taddr
, size_t len
, void* dst
);
120 void write_chunk(addr_t taddr
, size_t len
, const void* src
);
121 size_t chunk_align() { return 8; }
122 size_t chunk_max_size() { return 8; }
125 // Initialize this after procs, because in debug_module_t::reset() we
126 // enumerate processors, which segfaults if procs hasn't been initialized
128 debug_module_t debug_module
;
131 extern volatile bool ctrlc_pressed
;