1 // See LICENSE for license details.
15 // this class encapsulates the processors and memory in a RISC-V machine.
19 sim_t(const char* isa
, size_t _nprocs
, size_t mem_mb
,
20 const std::vector
<std::string
>& htif_args
);
23 // run the simulation to completion
27 void set_debug(bool value
);
28 void set_log(bool value
);
29 void set_histogram(bool value
);
30 void set_procs_debug(bool value
);
31 htif_isasim_t
* get_htif() { return htif
.get(); }
33 // returns the number of processors in this simulator
34 size_t num_cores() { return procs
.size(); }
35 processor_t
* get_core(size_t i
) { return procs
.at(i
); }
37 // read one of the system control registers
38 reg_t
get_scr(int which
);
41 std::unique_ptr
<htif_isasim_t
> htif
;
42 char* mem
; // main memory
43 size_t memsz
; // memory size in bytes
44 mmu_t
* debug_mmu
; // debug port into main memory
45 std::vector
<processor_t
*> procs
;
46 std::unique_ptr
<rom_device_t
> devicetree
;
49 processor_t
* get_core(const std::string
& i
);
50 void step(size_t n
); // step through simulation
51 static const size_t INTERLEAVE
= 5000;
52 static const size_t INSNS_PER_RTC_TICK
= 100; // 10 MHz clock for 1 BIPS core
58 bool histogram_enabled
; // provide a histogram of PCs
60 // memory-mapped I/O routines
61 bool mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
);
62 bool mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
);
63 void make_device_tree();
65 // presents a prompt for introspection into the simulation
68 // functions that help implement interactive()
69 void interactive_help(const std::string
& cmd
, const std::vector
<std::string
>& args
);
70 void interactive_quit(const std::string
& cmd
, const std::vector
<std::string
>& args
);
71 void interactive_run(const std::string
& cmd
, const std::vector
<std::string
>& args
, bool noisy
);
72 void interactive_run_noisy(const std::string
& cmd
, const std::vector
<std::string
>& args
);
73 void interactive_run_silent(const std::string
& cmd
, const std::vector
<std::string
>& args
);
74 void interactive_reg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
75 void interactive_fregs(const std::string
& cmd
, const std::vector
<std::string
>& args
);
76 void interactive_fregd(const std::string
& cmd
, const std::vector
<std::string
>& args
);
77 void interactive_pc(const std::string
& cmd
, const std::vector
<std::string
>& args
);
78 void interactive_mem(const std::string
& cmd
, const std::vector
<std::string
>& args
);
79 void interactive_str(const std::string
& cmd
, const std::vector
<std::string
>& args
);
80 void interactive_until(const std::string
& cmd
, const std::vector
<std::string
>& args
);
81 reg_t
get_reg(const std::vector
<std::string
>& args
);
82 reg_t
get_freg(const std::vector
<std::string
>& args
);
83 reg_t
get_mem(const std::vector
<std::string
>& args
);
84 reg_t
get_pc(const std::vector
<std::string
>& args
);
85 reg_t
get_tohost(const std::vector
<std::string
>& args
);
87 friend class htif_isasim_t
;
88 friend class processor_t
;
92 extern volatile bool ctrlc_pressed
;