1 // See LICENSE for license details.
8 #include "debug_module.h"
10 #include <fesvr/htif.h>
11 #include <fesvr/context.h>
17 class remote_bitbang_t
;
19 // this class encapsulates the processors and memory in a RISC-V machine.
20 class sim_t
: public htif_t
, public simif_t
23 sim_t(const char* isa
, size_t _nprocs
, bool halted
, reg_t start_pc
,
24 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
,
25 const std::vector
<std::string
>& args
, const std::vector
<int> hartids
,
26 unsigned progsize
, unsigned max_bus_master_bits
, bool require_authentication
);
29 // run the simulation to completion
31 void set_debug(bool value
);
32 void set_log(bool value
);
33 void set_histogram(bool value
);
34 void set_procs_debug(bool value
);
35 void set_remote_bitbang(remote_bitbang_t
* remote_bitbang
) {
36 this->remote_bitbang
= remote_bitbang
;
38 const char* get_dts() { if (dts
.empty()) reset(); return dts
.c_str(); }
39 processor_t
* get_core(size_t i
) { return procs
.at(i
); }
40 unsigned nprocs() const { return procs
.size(); }
42 // Callback for processors to let the simulation know they were reset.
43 void proc_reset(unsigned id
);
46 std::vector
<std::pair
<reg_t
, mem_t
*>> mems
;
47 mmu_t
* debug_mmu
; // debug port into main memory
48 std::vector
<processor_t
*> procs
;
51 std::unique_ptr
<rom_device_t
> boot_rom
;
52 std::unique_ptr
<clint_t
> clint
;
55 processor_t
* get_core(const std::string
& i
);
56 void step(size_t n
); // step through simulation
57 static const size_t INTERLEAVE
= 5000;
58 static const size_t INSNS_PER_RTC_TICK
= 100; // 10 MHz clock for 1 BIPS core
59 static const size_t CPU_HZ
= 1000000000; // 1GHz CPU
64 bool histogram_enabled
; // provide a histogram of PCs
65 remote_bitbang_t
* remote_bitbang
;
67 // memory-mapped I/O routines
68 char* addr_to_mem(reg_t addr
);
69 bool mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
);
70 bool mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
);
73 // presents a prompt for introspection into the simulation
76 // functions that help implement interactive()
77 void interactive_help(const std::string
& cmd
, const std::vector
<std::string
>& args
);
78 void interactive_quit(const std::string
& cmd
, const std::vector
<std::string
>& args
);
79 void interactive_run(const std::string
& cmd
, const std::vector
<std::string
>& args
, bool noisy
);
80 void interactive_run_noisy(const std::string
& cmd
, const std::vector
<std::string
>& args
);
81 void interactive_run_silent(const std::string
& cmd
, const std::vector
<std::string
>& args
);
82 void interactive_reg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
83 void interactive_freg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
84 void interactive_fregs(const std::string
& cmd
, const std::vector
<std::string
>& args
);
85 void interactive_fregd(const std::string
& cmd
, const std::vector
<std::string
>& args
);
86 void interactive_pc(const std::string
& cmd
, const std::vector
<std::string
>& args
);
87 void interactive_mem(const std::string
& cmd
, const std::vector
<std::string
>& args
);
88 void interactive_str(const std::string
& cmd
, const std::vector
<std::string
>& args
);
89 void interactive_until(const std::string
& cmd
, const std::vector
<std::string
>& args
);
90 reg_t
get_reg(const std::vector
<std::string
>& args
);
91 freg_t
get_freg(const std::vector
<std::string
>& args
);
92 reg_t
get_mem(const std::vector
<std::string
>& args
);
93 reg_t
get_pc(const std::vector
<std::string
>& args
);
95 friend class processor_t
;
97 friend class debug_module_t
;
100 friend void sim_thread_main(void*);
107 void read_chunk(addr_t taddr
, size_t len
, void* dst
);
108 void write_chunk(addr_t taddr
, size_t len
, const void* src
);
109 size_t chunk_align() { return 8; }
110 size_t chunk_max_size() { return 8; }
113 // Initialize this after procs, because in debug_module_t::reset() we
114 // enumerate processors, which segfaults if procs hasn't been initialized
116 debug_module_t debug_module
;
119 extern volatile bool ctrlc_pressed
;