1 // See LICENSE for license details.
6 #include <fesvr/option_parser.h>
16 fprintf(stderr
, "usage: spike [host options] <target program> [target options]\n");
17 fprintf(stderr
, "Host Options:\n");
18 fprintf(stderr
, " -p <n> Simulate <n> processors\n");
19 fprintf(stderr
, " -m <n> Provide <n> MB of target memory\n");
20 fprintf(stderr
, " -d Interactive debug mode\n");
21 fprintf(stderr
, " -h Print this help message\n");
22 fprintf(stderr
, " -h Print this help message\n");
23 fprintf(stderr
, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
24 fprintf(stderr
, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
25 fprintf(stderr
, " --l2=<S>:<W>:<B> B both powers of 2).\n");
29 int main(int argc
, char** argv
)
34 std::unique_ptr
<icache_sim_t
> ic
;
35 std::unique_ptr
<dcache_sim_t
> dc
;
36 std::unique_ptr
<cache_sim_t
> l2
;
38 option_parser_t parser
;
40 parser
.option('d', 0, 0, [&](const char* s
){debug
= true;});
41 parser
.option('p', 0, 1, [&](const char* s
){nprocs
= atoi(s
);});
42 parser
.option('m', 0, 1, [&](const char* s
){mem_mb
= atoi(s
);});
43 parser
.option(0, "ic", 1, [&](const char* s
){ic
.reset(new icache_sim_t(s
));});
44 parser
.option(0, "dc", 1, [&](const char* s
){dc
.reset(new dcache_sim_t(s
));});
45 parser
.option(0, "l2", 1, [&](const char* s
){l2
.reset(cache_sim_t::construct(s
, "L2$"));});
47 auto argv1
= parser
.parse(argv
);
50 std::vector
<std::string
> htif_args(argv1
, (const char*const*)argv
+ argc
);
51 sim_t
s(nprocs
, mem_mb
, htif_args
);
53 if (ic
&& l2
) ic
->set_miss_handler(&*l2
);
54 if (dc
&& l2
) dc
->set_miss_handler(&*l2
);
55 for (size_t i
= 0; i
< nprocs
; i
++)
57 if (ic
) s
.get_core(i
)->get_mmu()->register_memtracer(&*ic
);
58 if (dc
) s
.get_core(i
)->get_mmu()->register_memtracer(&*dc
);