rename sv vlen to sv voffs, add csr and reg tables

[riscv-isa-sim.git] / riscv / sv.cc

#include "sv.h"

sv_reg_csr_entry sv_csrs[SV_CSR_SZ];
sv_reg_entry sv_int_tb[NXPR];
sv_reg_entry sv_fp_tb[NFPR];
sv_pred_csr_entry sv_pred_csrs[SV_CSR_SZ];
sv_pred_entry sv_pred_tb[NXPR];