4 sv_reg_csr_entry sv_csrs
[SV_CSR_SZ
];
5 sv_reg_entry sv_int_tb
[NXPR
];
6 sv_reg_entry sv_fp_tb
[NFPR
];
7 sv_pred_csr_entry sv_pred_csrs
[SV_CSR_SZ
];
8 sv_pred_entry sv_pred_tb
[NXPR
];
10 bool sv_check_reg(bool intreg
, uint64_t reg
)
23 // XXX raise exception
25 if (r
->active
&& r
->isvec
)
32 uint64_t sv_insn_t::remap(uint64_t reg
, bool isint
)