4 sv_pred_entry
* sv_insn_t::get_predentry(uint64_t reg
, bool intreg
)
6 // okaay so first determine which map to use. intreg is passed
7 // in (ultimately) from id_regs.py's examination of the use of
8 // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
9 // in from sv_insn_t::fimap...
13 return &p
->get_state()->sv_pred_int_tb
[reg
];
17 return &p
->get_state()->sv_pred_fp_tb
[reg
];
21 sv_reg_entry
* sv_insn_t::get_regentry(uint64_t reg
, bool intreg
)
23 // okaay so first determine which map to use. intreg is passed
24 // in (ultimately) from id_regs.py's examination of the use of
25 // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
26 // in from sv_insn_t::fimap...
30 return &p
->get_state()->sv_int_tb
[reg
];
34 return &p
->get_state()->sv_fp_tb
[reg
];
38 bool sv_insn_t::sv_check_reg(bool intreg
, uint64_t reg
)
40 sv_reg_entry
*r
= get_regentry(reg
, intreg
);
43 // XXX raise exception
45 if (r
->active
&& r
->isvec
)
47 fprintf(stderr
, "checkreg: %ld active\n", reg
);
53 /* this is the "remap" function. note that registers can STILL BE REDIRECTED
54 * yet NOT BE MARKED AS A VECTOR.
56 * reg 5 -> active=false, regidx=XX, isvec=XX -> returns 5
57 * reg 5 -> active=true , regidx=35, isvec=false -> returns 35
58 * reg 5 -> active=true , regidx=35, isvec=true -> returns 35 *PLUS LOOP*
60 * so it is possible for example to use the remap system for C instructions
61 * to get access to the *full* range of registers x0..x63 (yes 63 because
62 * SV doubles both the int and fp regfile sizes), by setting
63 * "active=true, isvec=false" for any of x8..x15
65 * where "active=true, isvec=true" this is the "expected" behaviour
66 * of SV. it's "supposed" to "just" be a vectorisation API. it isn't:
67 * it's quite a bit more.
69 uint64_t sv_insn_t::remap(uint64_t reg
, bool intreg
, int &voffs
, uint64_t &pred
)
71 // okaay so first determine which map to use. intreg is passed
72 // in (ultimately) from id_regs.py's examination of the use of
73 // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
74 // in from sv_insn_t::fimap...
75 sv_reg_entry
*r
= get_regentry(reg
, intreg
);
77 // next we check if this entry is active. if not, the register
78 // is not being "redirected", so just return the actual reg.
81 vloop_continue
= false;
82 return reg
; // not active: return as-is
85 // next we go through the lookup table. *THIS* is why the
86 // sv_reg_entry table is 32 entries (5-bit) *NOT* 6 bits
87 // the *KEY* (reg) is 5-bit, the *VALUE* (actual target reg) is 6-bit
88 // XXX TODO: must actually double NXPR and NXFR in processor.h to cope!!
91 // now we determine if this is a scalar/vector: if it's scalar
92 // we return the re-mapped register...
93 if (!r
->isvec
) // scalar
95 // reg remapped even as scalar
96 vloop_continue
= false;
97 return predicated(reg
, voffs
, pred
); // returns x0 if pred bit false
100 // aaand now, as it's a "vector", FINALLY we can add on the loop-offset
101 // which was passed in to the sv_insn_t constructor (by reference)
102 // and, at last, we have "parallelism" a la contiguous registers.
103 reg
+= voffs
; // wheww :)
105 // before returning, put the register through the predication wringer.
106 // this will return x0 if predication is false
107 reg
= predicated(reg
, voffs
, pred
);
109 // however... before returning, we increment the loop-offset for
110 // this particular register, so that on the next loop the next
111 // contiguous register will be used.
116 /* gets the predication value (if active). returns all-1s if not active
117 * also returns whether zeroing is enabled/disabled for this register.
119 * uses the same sort of lookup logic as remap:
121 * - first thing to note is, there is one CSR table for FP and one for INT
122 * (so, FP regs can be predicated separately from INT ones)
123 * - redirection occurs if the CSR entry for the register is "active".
124 * - inversion of the predication can be set (so it's possible to have
125 * the same actual register value be unchanged yet be referred to by
126 * *TWO* redirections, one with inversion, one with not).
128 * note that this function *actually* returns the value of the (integer)
129 * register file, hence why processor_t has to be passed in
131 * note also that *even scalar* ops will be predicated (i.e. if a register
132 * has been set active=true and isvec=false in sv_int_tb or sv_fp_tb).
133 * the way to ensure that scalar ops are not predicated is: set VLEN=0,
134 * set active=false in sv_int_tb/sv_fp_tb for that register, or switch off
135 * the predication for that register (sv_pred_int_tb/sv_pred_fb_tb).
137 * note also that the hard limit on SV maximum vector length is actually
138 * down to the number of bits in the predication i.e. the bitwidth of integer
139 * registers (i.e. XLEN bits).
141 reg_t
sv_insn_t::predicate(uint64_t reg
, bool intreg
, bool &zeroing
)
143 sv_pred_entry
*r
= get_predentry(reg
, intreg
);
146 return ~0x0; // not active: return all-1s (unconditional "on")
150 reg_t predicate
= READ_REG(reg
); // macros go through processor_t state
158 uint64_t sv_insn_t::predicated(uint64_t reg
, int offs
, uint64_t pred
)
160 if (pred
& (1<<offs
))
164 fprintf(stderr
, "predication %ld %d %lx\n", reg
, offs
, pred
);