riscv/sv.cc

   1 #include "sv.h"
   2 #include "sv_decode.h"
   3
   4 sv_pred_entry* sv_insn_t::get_predentry(uint64_t reg, bool intreg)
   5 {
   6   // okaay so first determine which map to use.  intreg is passed
   7   // in (ultimately) from id_regs.py's examination of the use of
   8   // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
   9   // in from sv_insn_t::fimap...
  10   sv_pred_entry *r;
  11   if (intreg)
  12   {
  13     return &p->get_state()->sv_pred_int_tb[reg];
  14   }
  15   else
  16   {
  17     return &p->get_state()->sv_pred_fp_tb[reg];
  18   }
  19 }
  20
  21 sv_reg_entry* sv_insn_t::get_regentry(uint64_t reg, bool intreg)
  22 {
  23   // okaay so first determine which map to use.  intreg is passed
  24   // in (ultimately) from id_regs.py's examination of the use of
  25   // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
  26   // in from sv_insn_t::fimap...
  27   sv_reg_entry *r;
  28   if (intreg)
  29   {
  30     return &p->get_state()->sv_int_tb[reg];
  31   }
  32   else
  33   {
  34     return &p->get_state()->sv_fp_tb[reg];
  35   }
  36 }
  37
  38 bool sv_insn_t::sv_check_reg(bool intreg, uint64_t reg)
  39 {
  40   sv_reg_entry *r = get_regentry(reg, intreg);
  41   if (r->elwidth != 0)
  42   {
  43     // XXX raise exception
  44   }
  45   if (r->active && r->isvec)
  46   {
  47     return true;
  48   }
  49   return false;
  50 }
  51
  52 /* this is the "remap" function.  note that registers can STILL BE REDIRECTED
  53  * yet NOT BE MARKED AS A VECTOR.
  54  *
  55  * reg 5 -> active=false, regidx=XX, isvec=XX     -> returns 5
  56  * reg 5 -> active=true , regidx=35, isvec=false  -> returns 35
  57  * reg 5 -> active=true , regidx=35, isvec=true   -> returns 35 *PLUS LOOP*
  58  *
  59  * so it is possible for example to use the remap system for C  instructions
  60  * to get access to the *full* range of registers x0..x63 (yes 63 because
  61  * SV doubles both the int and fp regfile sizes), by setting
  62  * "active=true, isvec=false" for any of x8..x15
  63  *
  64  * where "active=true, isvec=true" this is the "expected" behaviour
  65  * of SV.  it's "supposed" to "just" be a vectorisation API. it isn't:
  66  * it's quite a bit more.
  67  */
  68 uint64_t sv_insn_t::remap(uint64_t reg, bool intreg, int &voffs)
  69 {
  70   // okaay so first determine which map to use.  intreg is passed
  71   // in (ultimately) from id_regs.py's examination of the use of
  72   // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
  73   // in from sv_insn_t::fimap...
  74   sv_reg_entry *r = get_regentry(reg, intreg);
  75
  76   // next we check if this entry is active.  if not, the register
  77   // is not being "redirected", so just return the actual reg.
  78   if (!r->active)
  79   {
  80     return reg; // not active: return as-is
  81   }
  82
  83   // next we go through the lookup table.  *THIS* is why the
  84   // sv_reg_entry table is 32 entries (5-bit) *NOT* 6 bits
  85   // the *KEY* (reg) is 5-bit, the *VALUE* (actual target reg) is 6-bit
  86   // XXX TODO: must actually double NXPR and NXFR in processor.h to cope!!
  87   reg = r->regidx;
  88
  89   // now we determine if this is a scalar/vector: if it's scalar
  90   // we return the re-mapped register...
  91   if (!r->isvec) // scalar
  92   {
  93     return reg; // ... remapped at this point...
  94   }
  95
  96   // aaand now, as it's a "vector", FINALLY we can add on the loop-offset
  97   // which was passed in to the sv_insn_t constructor (by reference)
  98   // and, at last, we have "parallelism" a la contiguous registers.
  99   reg += voffs; // wheww :)
 100
 101   // however... before returning, we increment the loop-offset for
 102   // this particular register, so that on the next loop the next
 103   // contiguous register will be used.
 104   voffs += 1;
 105   return reg;
 106 }
 107
 108 /* gets the predication value (if active).  returns all-1s if not active
 109  * also returns whether zeroing is enabled/disabled for this register.
 110  *
 111  * uses the same sort of lookup logic as remap:
 112  *
 113  * - first thing to note is, there is one CSR table for FP and one for INT
 114  *   (so, FP regs can be predicated separately from INT ones)
 115  * - redirection occurs if the CSR entry for the register is "active".
 116  * - inversion of the predication can be set (so it's possible to have
 117  *   the same actual register value be unchanged yet be referred to by
 118  *   *TWO* redirections, one with inversion, one with not).
 119  *
 120  * note that this function *actually* returns the value of the (integer)
 121  * register file, hence why processor_t has to be passed in
 122  *
 123  * note also that *even scalar* ops will be predicated (i.e. if a register
 124  * has been set active=true and isvec=false in sv_int_tb or sv_fp_tb).
 125  * the way to ensure that scalar ops are not predicated is: set VLEN=0,
 126  * set active=false in sv_int_tb/sv_fp_tb for that register, or switch off
 127  * the predication for that register (sv_pred_int_tb/sv_pred_fb_tb).
 128  *
 129  * note also that the hard limit on SV maximum vector length is actually
 130  * down to the number of bits in the predication i.e. the bitwidth of integer
 131  * registers (i.e. XLEN bits).
 132  */
 133 reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
 134 {
 135   sv_pred_entry *r = get_predentry(reg, intreg);
 136   if (!r->active)
 137   {
 138     return ~0x0; // not active: return all-1s (unconditional "on")
 139   }
 140   zeroing = r->zero;
 141   reg = r->regidx;
 142   reg_t predicate = READ_REG(reg); // macros go through processor_t state
 143   if (r->inv)
 144   {
 145     return ~predicate;
 146   }
 147   return predicate;
 148 }