riscv/sv.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SIMPLE_V_H
   4 #define _RISCV_SIMPLE_V_H
   5
   6 // this table is for the CSRs (4? for RV32E, 16 for other types)
   7 // it's a CAM that's used to generate 2 tables (below)
   8 // just as in RV, writing to entries in this CAM *clears*
   9 // all entries with a higher index
  10 typedef struct {
  11     unsigned int type   : 1; // 0=INT, 1=FP
  12     unsigned int regkey : 5; // 5 bits
  13     unsigned int elwidth: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
  14     unsigned int regidx : 6; // yes 6 bits
  15     unsigned int isvec  : 1; // vector=1, scalar=0
  16     unsigned int packed : 1; // Packed SIMD=1
  17 } sv_reg_csr_entry;
  18
  19 // this is the "unpacked" table, generated from the CAM above
  20 // there are 2 of them: one for FP, one for INT regs.
  21 // one sv_reg_entry is required per FP *and* per INT reg.
  22 // note that regidx is 6 bits however we actually only have
  23 // 32 entries.  reason: the *actual* number of registers is doubled
  24 // in SV however the instruction is STILL ONLY 5 BITS.
  25 typedef struct {
  26     unsigned int elwidth: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
  27     unsigned int regidx : 6; // yes 6 bits.
  28     unsigned int isvec  : 1; // vector=1, scalar=0
  29     unsigned int packed : 1; // Packed SIMD=1
  30     unsigned int active : 1; // enabled=1, disabled=0
  31 } sv_reg_entry;
  32
  33 typedef struct {
  34     unsigned int type  : 1; // 0=INT, 1=FP
  35     unsigned int regkey: 5; // 5 bits:
  36     unsigned int zero  : 1; // zeroing=1, skipping=0
  37     unsigned int inv   : 1; // inversion=1
  38     unsigned int regidx: 6; // 6 bits
  39     unsigned int active: 1; // enabled=1, disabled=0
  40 } sv_pred_csr_entry;
  41
  42 typedef struct {
  43     unsigned int regkey: 5; // 5 bits:
  44     unsigned int zero  : 1; // zeroing=1, skipping=0
  45     unsigned int inv   : 1; // inversion=1
  46     unsigned int regidx: 6; // 6 bits
  47     unsigned int active: 1; // enabled=1, disabled=0
  48 } sv_pred_entry;
  49
  50 #endif