Instructions are no longer member functions
[riscv-isa-sim.git] / riscv / trap.h
1 // See LICENSE for license details.
2
3 #ifndef _RISCV_TRAP_H
4 #define _RISCV_TRAP_H
5
6 #include "decode.h"
7
8 class state_t;
9
10 class trap_t
11 {
12 public:
13 trap_t(reg_t which) : which(which) {}
14 virtual const char* name();
15 virtual void side_effects(state_t* state) {}
16 reg_t cause() { return which; }
17 private:
18 char _name[16];
19 reg_t which;
20 };
21
22 class mem_trap_t : public trap_t
23 {
24 public:
25 mem_trap_t(reg_t which, reg_t badvaddr)
26 : trap_t(which), badvaddr(badvaddr) {}
27 void side_effects(state_t* state);
28 private:
29 reg_t badvaddr;
30 };
31
32 #define DECLARE_TRAP(n, x) class trap_##x : public trap_t { \
33 public: \
34 trap_##x() : trap_t(n) {} \
35 const char* name() { return "trap_"#x; } \
36 };
37
38 #define DECLARE_MEM_TRAP(n, x) class trap_##x : public mem_trap_t { \
39 public: \
40 trap_##x(reg_t badvaddr) : mem_trap_t(n, badvaddr) {} \
41 const char* name() { return "trap_"#x; } \
42 };
43
44 DECLARE_TRAP(0, instruction_address_misaligned)
45 DECLARE_TRAP(1, instruction_access_fault)
46 DECLARE_TRAP(2, illegal_instruction)
47 DECLARE_TRAP(3, privileged_instruction)
48 DECLARE_TRAP(4, fp_disabled)
49 DECLARE_TRAP(5, reserved0)
50 DECLARE_TRAP(6, syscall)
51 DECLARE_TRAP(7, breakpoint)
52 DECLARE_MEM_TRAP(8, load_address_misaligned)
53 DECLARE_MEM_TRAP(9, store_address_misaligned)
54 DECLARE_MEM_TRAP(10, load_access_fault)
55 DECLARE_MEM_TRAP(11, store_access_fault)
56 DECLARE_TRAP(12, vector_disabled)
57 DECLARE_TRAP(13, vector_bank)
58 DECLARE_TRAP(14, vector_illegal_instruction)
59
60 #endif