rtl/vhdl/c4m_jtag_pkg.vhdl

   1 -- Package of jtag support code from the Chips4Makers project
   2 library ieee;
   3 use ieee.std_logic_1164.ALL;
   4
   5 package c4m_jtag is
   6   type TAPSTATE_TYPE is (
   7     TestLogicReset,
   8     RunTestIdle,
   9     SelectDRScan,
  10     SelectIRScan,
  11     Capture,
  12     Shift,
  13     Exit1,
  14     Pause,
  15     Exit2,
  16     Update
  17   );
  18   type SRIOMODE_TYPE is (
  19     SR_Through, -- Connect core signal to pad signals
  20     SR_2Pad,    -- Connect BD to pad
  21     SR_2Core,   -- Connect BD to core
  22     SR_Z        -- pad is high impedance
  23   );
  24   type SRSAMPLEMODE_TYPE is (
  25     SR_Normal,  -- No sampling or shifting
  26     SR_Sample,  -- Sample IO state in BD SR on rising edge of TCK
  27     SR_Update,  -- Update BD from SR on falling edge of TCK
  28     SR_Shift    -- Shift the BD SR
  29   );
  30
  31   component c4m_jtag_tap_fsm is
  32     port (
  33       -- The TAP signals
  34       TCK:      in std_logic;
  35       TMS:      in std_logic;
  36       TRST_N:   in std_logic;
  37
  38       -- The state outputs
  39       STATE:    out TAPSTATE_TYPE;
  40       NEXT_STATE: out TAPSTATE_TYPE;
  41       DRSTATE:  out std_logic;
  42       IRSTATE:  out std_logic
  43     );
  44   end component c4m_jtag_tap_fsm;
  45
  46   component c4m_jtag_irblock is
  47     generic (
  48       IR_WIDTH: integer := 2
  49     );
  50     port (
  51       -- needed TAP signals
  52       TCK:      in std_logic;
  53       TDI:      in std_logic;
  54       TDO:      out std_logic;
  55
  56       -- JTAG state
  57       STATE:    in TAPSTATE_TYPE;
  58       NEXT_STATE: in TAPSTATE_TYPE;
  59       IRSTATE:  in std_logic;
  60
  61       -- instruction register
  62       IR:       out std_logic_vector(IR_WIDTH-1 downto 0)
  63     );
  64   end component c4m_jtag_irblock;
  65
  66   component c4m_jtag_idblock is
  67     generic (
  68       IR_WIDTH:         integer := 2;
  69
  70       PART_NUMBER:      std_logic_vector(15 downto 0);
  71       VERSION:          std_logic_vector(3 downto 0) := "0000";
  72       MANUFACTURER:     std_logic_vector(10 downto 0)
  73     );
  74     port (
  75       -- needed TAP signals
  76       TCK:      in std_logic;
  77       TDI:      in std_logic;
  78       TDO:      out std_logic;
  79
  80       -- JTAG state
  81       STATE:    in TAPSTATE_TYPE;
  82       NEXT_STATE: in TAPSTATE_TYPE;
  83       DRSTATE:  in std_logic;
  84
  85       -- The instruction
  86       IR:       in std_logic_vector(IR_WIDTH-1 downto 0)
  87     );
  88   end component c4m_jtag_idblock;
  89
  90   component c4m_jtag_iocell is
  91     port (
  92       -- core connections
  93       CORE_IN:  out std_logic;
  94       CORE_OUT: in std_logic;
  95       CORE_EN:  in std_logic;
  96
  97       -- pad connections
  98       PAD_IN:   in std_logic;
  99       PAD_OUT:  out std_logic;
 100       PAD_EN:   out std_logic;
 101
 102       -- BD shift register
 103       BDSR_IN:  in std_logic;
 104       BDSR_OUT: out std_logic;
 105
 106       -- Mode of I/O cell
 107       IOMODE:   in SRIOMODE_TYPE;
 108       SAMPLEMODE: in SRSAMPLEMODE_TYPE;
 109       TCK:      in std_logic
 110     );
 111   end component c4m_jtag_iocell;
 112
 113   component c4m_jtag_ioblock is
 114     generic (
 115       IR_WIDTH: integer := 2;
 116       IOS:      integer := 1
 117     );
 118     port (
 119       -- needed TAP signals
 120       TCK:      in std_logic;
 121       TDI:      in std_logic;
 122       TDO:      out std_logic;
 123
 124       -- JTAG state
 125       STATE:    in TAPSTATE_TYPE;
 126       NEXT_STATE: in TAPSTATE_TYPE;
 127       DRSTATE:  in std_logic;
 128
 129       -- The instruction
 130       IR:       in std_logic_vector(IR_WIDTH-1 downto 0);
 131
 132       -- The I/O access ports
 133       CORE_OUT: in std_logic_vector(IOS-1 downto 0);
 134       CORE_IN:  out std_logic_vector(IOS-1 downto 0);
 135       CORE_EN:  in std_logic_vector(IOS-1 downto 0);
 136
 137       -- The pad connections
 138       PAD_OUT:  out std_logic_vector(IOS-1 downto 0);
 139       PAD_IN:   in std_logic_vector(IOS-1 downto 0);
 140       PAD_EN:   out std_logic_vector(IOS-1 downto 0)
 141     );
 142   end component c4m_jtag_ioblock;
 143
 144   component c4m_jtag_tap_controller is
 145     generic (
 146       IR_WIDTH: integer := 2;
 147       IOS:      integer := 1;
 148
 149       VERSION:  std_logic_vector(3 downto 0) := "0000"
 150     );
 151     port (
 152       -- The TAP signals
 153       TCK:      in std_logic;
 154       TMS:      in std_logic;
 155       TDI:      in std_logic;
 156       TDO:      out std_logic;
 157       TRST_N:   in std_logic;
 158
 159       -- The FSM state indicators
 160       STATE:    out TAPSTATE_TYPE;
 161       NEXT_STATE: out TAPSTATE_TYPE;
 162       DRSTATE:  out std_logic;
 163
 164       -- The Instruction Register
 165       IR:       out std_logic_vector(IR_WIDTH-1 downto 0);
 166
 167       -- The I/O access ports
 168       CORE_IN:  out std_logic_vector(IOS-1 downto 0);
 169       CORE_EN:  in std_logic_vector(IOS-1 downto 0);
 170       CORE_OUT: in std_logic_vector(IOS-1 downto 0);
 171
 172       -- The pad connections
 173       PAD_IN:   in std_logic_vector(IOS-1 downto 0);
 174       PAD_EN:   out std_logic_vector(IOS-1 downto 0);
 175       PAD_OUT:  out std_logic_vector(IOS-1 downto 0)
 176     );
 177   end component c4m_jtag_tap_controller;
 178
 179   function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector;
 180   function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector;
 181   function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector;
 182   function c4m_jtag_cmd_extest(width: integer) return std_logic_vector;
 183 end c4m_jtag;
 184
 185 package body c4m_jtag is
 186   function c4m_jtag_cmd_bypass(width: integer) return std_logic_vector is
 187     variable return_vector: std_logic_vector(width-1 downto 0);
 188   begin
 189     return_vector := (others => '1');
 190     return return_vector;
 191   end;
 192
 193   function c4m_jtag_cmd_idcode(width: integer) return std_logic_vector is
 194     variable return_vector: std_logic_vector(width-1 downto 0);
 195   begin
 196     return_vector := (0 => '1', others => '0');
 197     return return_vector;
 198   end;
 199
 200   function c4m_jtag_cmd_samplepreload(width: integer) return std_logic_vector is
 201     variable return_vector: std_logic_vector(width-1 downto 0);
 202   begin
 203     return_vector := (1 => '1', others => '0');
 204     return return_vector;
 205   end;
 206
 207   function c4m_jtag_cmd_extest(width: integer) return std_logic_vector is
 208     variable return_vector: std_logic_vector(width-1 downto 0);
 209   begin
 210     return_vector := (others => '0');
 211     return return_vector;
 212   end;
 213 end package body;