projects / riscv-isa-sim.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Rip out RVC for now
[riscv-isa-sim.git] / rvc / insns / c_lw.h
1 require_rvc;
2 CRDS = mmu.load_int32(CRS1S+CIMM5*4);
Simple-V augmented version of spike