1 // See LICENSE for license details.
10 struct : public arg_t
{
11 std::string
to_string(insn_t insn
) const {
12 return std::to_string((int)insn
.i_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
16 struct : public arg_t
{
17 std::string
to_string(insn_t insn
) const {
18 return std::to_string((int)insn
.s_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
22 struct : public arg_t
{
23 std::string
to_string(insn_t insn
) const {
24 return std::string("(") + xpr_name
[insn
.rs1()] + ')';
28 struct : public arg_t
{
29 std::string
to_string(insn_t insn
) const {
30 return xpr_name
[insn
.rd()];
34 struct : public arg_t
{
35 std::string
to_string(insn_t insn
) const {
36 return xpr_name
[insn
.rs1()];
40 struct : public arg_t
{
41 std::string
to_string(insn_t insn
) const {
42 return xpr_name
[insn
.rs2()];
46 struct : public arg_t
{
47 std::string
to_string(insn_t insn
) const {
48 return fpr_name
[insn
.rd()];
52 struct : public arg_t
{
53 std::string
to_string(insn_t insn
) const {
54 return fpr_name
[insn
.rs1()];
58 struct : public arg_t
{
59 std::string
to_string(insn_t insn
) const {
60 return fpr_name
[insn
.rs2()];
64 struct : public arg_t
{
65 std::string
to_string(insn_t insn
) const {
66 return fpr_name
[insn
.rs3()];
70 struct : public arg_t
{
71 std::string
to_string(insn_t insn
) const {
74 #define DECLARE_CSR(name, num) case num: return #name;
77 default: return "unknown";
82 struct : public arg_t
{
83 std::string
to_string(insn_t insn
) const {
84 return std::to_string((int)insn
.i_imm());
88 struct : public arg_t
{
89 std::string
to_string(insn_t insn
) const {
91 s
<< std::hex
<< "0x" << ((uint32_t)insn
.u_imm() >> 12);
96 struct : public arg_t
{
97 std::string
to_string(insn_t insn
) const {
98 return std::to_string(insn
.rs1());
102 struct : public arg_t
{
103 std::string
to_string(insn_t insn
) const {
105 int32_t target
= insn
.sb_imm();
106 char sign
= target
>= 0 ? '+' : '-';
107 s
<< "pc " << sign
<< ' ' << abs(target
);
112 struct : public arg_t
{
113 std::string
to_string(insn_t insn
) const {
115 int32_t target
= insn
.uj_imm();
116 char sign
= target
>= 0 ? '+' : '-';
117 s
<< "pc " << sign
<< std::hex
<< " 0x" << abs(target
);
122 struct : public arg_t
{
123 std::string
to_string(insn_t insn
) const {
124 return xpr_name
[insn
.rvc_rs1()];
128 struct : public arg_t
{
129 std::string
to_string(insn_t insn
) const {
130 return xpr_name
[insn
.rvc_rs2()];
134 struct : public arg_t
{
135 std::string
to_string(insn_t insn
) const {
136 return xpr_name
[insn
.rvc_rs1s()];
140 struct : public arg_t
{
141 std::string
to_string(insn_t insn
) const {
142 return xpr_name
[insn
.rvc_rs2s()];
146 struct : public arg_t
{
147 std::string
to_string(insn_t insn
) const {
148 return xpr_name
[X_SP
];
152 struct : public arg_t
{
153 std::string
to_string(insn_t insn
) const {
154 return std::to_string((int)insn
.rvc_imm());
158 struct : public arg_t
{
159 std::string
to_string(insn_t insn
) const {
160 return std::to_string((int)insn
.rvc_addi4spn_imm());
164 struct : public arg_t
{
165 std::string
to_string(insn_t insn
) const {
166 return std::to_string((int)insn
.rvc_addi16sp_imm());
170 struct : public arg_t
{
171 std::string
to_string(insn_t insn
) const {
172 return std::to_string((int)insn
.rvc_lwsp_imm());
176 struct : public arg_t
{
177 std::string
to_string(insn_t insn
) const {
178 return std::to_string((int)(insn
.rvc_imm() & 0x3f));
182 struct : public arg_t
{
183 std::string
to_string(insn_t insn
) const {
185 s
<< std::hex
<< "0x" << (uint32_t)insn
.rvc_imm();
190 struct : public arg_t
{
191 std::string
to_string(insn_t insn
) const {
192 return std::to_string((int)insn
.rvc_lwsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
196 struct : public arg_t
{
197 std::string
to_string(insn_t insn
) const {
198 return std::to_string((int)insn
.rvc_ldsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
202 struct : public arg_t
{
203 std::string
to_string(insn_t insn
) const {
204 return std::to_string((int)insn
.rvc_swsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
208 struct : public arg_t
{
209 std::string
to_string(insn_t insn
) const {
210 return std::to_string((int)insn
.rvc_sdsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
214 struct : public arg_t
{
215 std::string
to_string(insn_t insn
) const {
216 return std::to_string((int)insn
.rvc_lw_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
220 struct : public arg_t
{
221 std::string
to_string(insn_t insn
) const {
222 return std::to_string((int)insn
.rvc_ld_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
226 struct : public arg_t
{
227 std::string
to_string(insn_t insn
) const {
229 int32_t target
= insn
.rvc_b_imm();
230 char sign
= target
>= 0 ? '+' : '-';
231 s
<< "pc " << sign
<< ' ' << abs(target
);
236 struct : public arg_t
{
237 std::string
to_string(insn_t insn
) const {
239 int32_t target
= insn
.rvc_j_imm();
240 char sign
= target
>= 0 ? '+' : '-';
241 s
<< "pc " << sign
<< ' ' << abs(target
);
246 std::string
disassembler_t::disassemble(insn_t insn
)
248 const disasm_insn_t
* disasm_insn
= lookup(insn
);
249 return disasm_insn
? disasm_insn
->to_string(insn
) : "unknown";
252 disassembler_t::disassembler_t()
254 const uint32_t mask_rd
= 0x1fUL
<< 7;
255 const uint32_t match_rd_ra
= 1UL << 7;
256 const uint32_t mask_rs1
= 0x1fUL
<< 15;
257 const uint32_t match_rs1_ra
= 1UL << 15;
258 const uint32_t mask_rs2
= 0x1fUL
<< 20;
259 const uint32_t mask_imm
= 0xfffUL
<< 20;
260 const uint32_t match_imm_1
= 1UL << 20;
261 const uint32_t mask_rvc_rs2
= 0x1fUL
<< 2;
262 const uint32_t mask_rvc_imm
= mask_rvc_rs2
| 0x1000UL
;
264 #define DECLARE_INSN(code, match, mask) \
265 const uint32_t match_##code = match; \
266 const uint32_t mask_##code = mask;
267 #include "encoding.h"
270 // explicit per-instruction disassembly
271 #define DISASM_INSN(name, code, extra, ...) \
272 add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
273 #define DEFINE_NOARG(code) \
274 add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
275 #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
276 #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
277 #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
278 #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
279 #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
280 #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
281 #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
282 #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
283 #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
284 #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
285 #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
286 #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
287 #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
288 #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
289 #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
290 #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
291 #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
292 #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
293 #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
308 DEFINE_XAMO(amoadd_w
)
309 DEFINE_XAMO(amoswap_w
)
310 DEFINE_XAMO(amoand_w
)
312 DEFINE_XAMO(amoxor_w
)
313 DEFINE_XAMO(amomin_w
)
314 DEFINE_XAMO(amomax_w
)
315 DEFINE_XAMO(amominu_w
)
316 DEFINE_XAMO(amomaxu_w
)
317 DEFINE_XAMO(amoadd_d
)
318 DEFINE_XAMO(amoswap_d
)
319 DEFINE_XAMO(amoand_d
)
321 DEFINE_XAMO(amoxor_d
)
322 DEFINE_XAMO(amomin_d
)
323 DEFINE_XAMO(amomax_d
)
324 DEFINE_XAMO(amominu_d
)
325 DEFINE_XAMO(amomaxu_d
)
338 add_insn(new disasm_insn_t("j", match_jal
, mask_jal
| mask_rd
, {&jump_target
}));
339 add_insn(new disasm_insn_t("jal", match_jal
| match_rd_ra
, mask_jal
| mask_rd
, {&jump_target
}));
340 add_insn(new disasm_insn_t("jal", match_jal
, mask_jal
, {&xrd
, &jump_target
}));
342 DEFINE_B1TYPE("beqz", beq
);
343 DEFINE_B1TYPE("bnez", bne
);
344 DEFINE_B1TYPE("bltz", blt
);
345 DEFINE_B1TYPE("bgez", bge
);
356 add_insn(new disasm_insn_t("ret", match_jalr
| match_rs1_ra
, mask_jalr
| mask_rd
| mask_rs1
| mask_imm
, {}));
357 DEFINE_I2TYPE("jr", jalr
);
358 add_insn(new disasm_insn_t("jalr", match_jalr
| match_rd_ra
, mask_jalr
| mask_rd
| mask_imm
, {&xrs1
}));
361 add_insn(new disasm_insn_t("nop", match_addi
, mask_addi
| mask_rd
| mask_rs1
| mask_imm
, {}));
362 add_insn(new disasm_insn_t(" - ", match_xor
, mask_xor
| mask_rd
| mask_rs1
| mask_rs2
, {})); // for machine-generated bubbles
363 DEFINE_I0TYPE("li", addi
);
364 DEFINE_I1TYPE("mv", addi
);
368 add_insn(new disasm_insn_t("seqz", match_sltiu
| match_imm_1
, mask_sltiu
| mask_imm
, {&xrd
, &xrs1
}));
370 add_insn(new disasm_insn_t("not", match_xori
| mask_imm
, mask_xori
| mask_imm
, {&xrd
, &xrs1
}));
376 DEFINE_I1TYPE("sext.w", addiw
);
386 add_insn(new disasm_insn_t("snez", match_sltu
, mask_sltu
| mask_rs1
, {&xrd
, &xrs2
}));
396 DEFINE_RTYPE(mulhsu
);
413 DEFINE_NOARG(ebreak
);
419 DEFINE_NOARG(fence_i
);
421 add_insn(new disasm_insn_t("csrr", match_csrrs
, mask_csrrs
| mask_rs1
, {&xrd
, &csr
}));
422 add_insn(new disasm_insn_t("csrw", match_csrrw
, mask_csrrw
| mask_rd
, {&csr
, &xrs1
}));
423 add_insn(new disasm_insn_t("csrs", match_csrrs
, mask_csrrs
| mask_rd
, {&csr
, &xrs1
}));
424 add_insn(new disasm_insn_t("csrc", match_csrrc
, mask_csrrc
| mask_rd
, {&csr
, &xrs1
}));
425 add_insn(new disasm_insn_t("csrwi", match_csrrwi
, mask_csrrwi
| mask_rd
, {&csr
, &zimm5
}));
426 add_insn(new disasm_insn_t("csrsi", match_csrrsi
, mask_csrrsi
| mask_rd
, {&csr
, &zimm5
}));
427 add_insn(new disasm_insn_t("csrci", match_csrrci
, mask_csrrci
| mask_rd
, {&csr
, &zimm5
}));
428 add_insn(new disasm_insn_t("csrrw", match_csrrw
, mask_csrrw
, {&xrd
, &csr
, &xrs1
}));
429 add_insn(new disasm_insn_t("csrrs", match_csrrs
, mask_csrrs
, {&xrd
, &csr
, &xrs1
}));
430 add_insn(new disasm_insn_t("csrrc", match_csrrc
, mask_csrrc
, {&xrd
, &csr
, &xrs1
}));
431 add_insn(new disasm_insn_t("csrrwi", match_csrrwi
, mask_csrrwi
, {&xrd
, &csr
, &zimm5
}));
432 add_insn(new disasm_insn_t("csrrsi", match_csrrsi
, mask_csrrsi
, {&xrd
, &csr
, &zimm5
}));
433 add_insn(new disasm_insn_t("csrrci", match_csrrci
, mask_csrrci
, {&xrd
, &csr
, &zimm5
}));
435 DEFINE_FRTYPE(fadd_s
);
436 DEFINE_FRTYPE(fsub_s
);
437 DEFINE_FRTYPE(fmul_s
);
438 DEFINE_FRTYPE(fdiv_s
);
439 DEFINE_FR1TYPE(fsqrt_s
);
440 DEFINE_FRTYPE(fmin_s
);
441 DEFINE_FRTYPE(fmax_s
);
442 DEFINE_FR3TYPE(fmadd_s
);
443 DEFINE_FR3TYPE(fmsub_s
);
444 DEFINE_FR3TYPE(fnmadd_s
);
445 DEFINE_FR3TYPE(fnmsub_s
);
446 DEFINE_FRTYPE(fsgnj_s
);
447 DEFINE_FRTYPE(fsgnjn_s
);
448 DEFINE_FRTYPE(fsgnjx_s
);
449 DEFINE_FR1TYPE(fcvt_s_d
);
450 DEFINE_XFTYPE(fcvt_s_l
);
451 DEFINE_XFTYPE(fcvt_s_lu
);
452 DEFINE_XFTYPE(fcvt_s_w
);
453 DEFINE_XFTYPE(fcvt_s_wu
);
454 DEFINE_XFTYPE(fcvt_s_wu
);
455 DEFINE_XFTYPE(fmv_s_x
);
456 DEFINE_FXTYPE(fcvt_l_s
);
457 DEFINE_FXTYPE(fcvt_lu_s
);
458 DEFINE_FXTYPE(fcvt_w_s
);
459 DEFINE_FXTYPE(fcvt_wu_s
);
460 DEFINE_FXTYPE(fclass_s
);
461 DEFINE_FXTYPE(fmv_x_s
);
462 DEFINE_FXTYPE(feq_s
);
463 DEFINE_FXTYPE(flt_s
);
464 DEFINE_FXTYPE(fle_s
);
466 DEFINE_FRTYPE(fadd_d
);
467 DEFINE_FRTYPE(fsub_d
);
468 DEFINE_FRTYPE(fmul_d
);
469 DEFINE_FRTYPE(fdiv_d
);
470 DEFINE_FR1TYPE(fsqrt_d
);
471 DEFINE_FRTYPE(fmin_d
);
472 DEFINE_FRTYPE(fmax_d
);
473 DEFINE_FR3TYPE(fmadd_d
);
474 DEFINE_FR3TYPE(fmsub_d
);
475 DEFINE_FR3TYPE(fnmadd_d
);
476 DEFINE_FR3TYPE(fnmsub_d
);
477 DEFINE_FRTYPE(fsgnj_d
);
478 DEFINE_FRTYPE(fsgnjn_d
);
479 DEFINE_FRTYPE(fsgnjx_d
);
480 DEFINE_FR1TYPE(fcvt_d_s
);
481 DEFINE_XFTYPE(fcvt_d_l
);
482 DEFINE_XFTYPE(fcvt_d_lu
);
483 DEFINE_XFTYPE(fcvt_d_w
);
484 DEFINE_XFTYPE(fcvt_d_wu
);
485 DEFINE_XFTYPE(fcvt_d_wu
);
486 DEFINE_XFTYPE(fmv_d_x
);
487 DEFINE_FXTYPE(fcvt_l_d
);
488 DEFINE_FXTYPE(fcvt_lu_d
);
489 DEFINE_FXTYPE(fcvt_w_d
);
490 DEFINE_FXTYPE(fcvt_wu_d
);
491 DEFINE_FXTYPE(fclass_d
);
492 DEFINE_FXTYPE(fmv_x_d
);
493 DEFINE_FXTYPE(feq_d
);
494 DEFINE_FXTYPE(flt_d
);
495 DEFINE_FXTYPE(fle_d
);
497 DISASM_INSN("ebreak", c_add
, mask_rd
| mask_rvc_rs2
, {});
498 add_insn(new disasm_insn_t("ret", match_c_li
| match_rd_ra
, mask_c_li
| mask_rd
| mask_rvc_imm
, {}));
499 DISASM_INSN("jr", c_li
, mask_rvc_imm
, {&rvc_rs1
});
500 DISASM_INSN("jalr", c_lui
, mask_rvc_imm
, {&rvc_rs1
});
501 DISASM_INSN("nop", c_addi
, mask_rd
| mask_rvc_imm
, {});
502 DISASM_INSN("addi", c_addi16sp
, mask_rd
, {&rvc_sp
, &rvc_sp
, &rvc_addi16sp_imm
});
503 DISASM_INSN("addi", c_addi4spn
, 0, {&rvc_rs1s
, &rvc_sp
, &rvc_addi4spn_imm
});
504 DISASM_INSN("li", c_li
, 0, {&xrd
, &rvc_imm
});
505 DISASM_INSN("lui", c_lui
, 0, {&xrd
, &rvc_uimm
});
506 DISASM_INSN("addi", c_addi
, 0, {&xrd
, &xrd
, &rvc_imm
});
507 DISASM_INSN("addiw", c_addiw
, 0, {&xrd
, &xrd
, &rvc_imm
});
508 DISASM_INSN("slli", c_slli
, 0, {&xrd
, &rvc_shamt
});
509 DISASM_INSN("mv", c_mv
, 0, {&xrd
, &rvc_rs2
});
510 DISASM_INSN("add", c_add
, 0, {&xrd
, &xrd
, &rvc_rs2
});
511 DISASM_INSN("addw", c_addw
, 0, {&rvc_rs1s
, &rvc_rs1s
, &rvc_rs2s
});
512 DISASM_INSN("sub", c_sub
, 0, {&rvc_rs1s
, &rvc_rs1s
, &rvc_rs2s
});
513 DISASM_INSN("subw", c_subw
, 0, {&rvc_rs1s
, &rvc_rs1s
, &rvc_rs2s
});
514 DISASM_INSN("and", c_and
, 0, {&rvc_rs1s
, &rvc_rs1s
, &rvc_rs2s
});
515 DISASM_INSN("or", c_or
, 0, {&rvc_rs1s
, &rvc_rs1s
, &rvc_rs2s
});
516 DISASM_INSN("xor", c_xor
, 0, {&rvc_rs1s
, &rvc_rs1s
, &rvc_rs2s
});
517 DISASM_INSN("lw", c_lwsp
, 0, {&xrd
, &rvc_lwsp_address
});
518 DISASM_INSN("flw", c_flwsp
, 0, {&xrd
, &rvc_lwsp_address
});
519 DISASM_INSN("sw", c_swsp
, 0, {&rvc_rs2
, &rvc_swsp_address
});
520 DISASM_INSN("fsw", c_fswsp
, 0, {&rvc_rs2
, &rvc_swsp_address
});
521 DISASM_INSN("lw", c_lw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
522 DISASM_INSN("flw", c_flw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
523 DISASM_INSN("sw", c_sw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
524 DISASM_INSN("fsw", c_fsw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
525 DISASM_INSN("beqz", c_beqz
, 0, {&rvc_rs1s
, &rvc_branch_target
});
526 DISASM_INSN("bnez", c_bnez
, 0, {&rvc_rs1s
, &rvc_branch_target
});
527 DISASM_INSN("j", c_j
, 0, {&rvc_jump_target
});
529 // provide a default disassembly for all instructions as a fallback
530 #define DECLARE_INSN(code, match, mask) \
531 add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
532 #include "encoding.h"
536 const disasm_insn_t
* disassembler_t::lookup(insn_t insn
)
538 size_t idx
= insn
.bits() % HASH_SIZE
;
539 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
540 if(*chain
[idx
][j
] == insn
)
541 return chain
[idx
][j
];
544 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
545 if(*chain
[idx
][j
] == insn
)
546 return chain
[idx
][j
];
551 void disassembler_t::add_insn(disasm_insn_t
* insn
)
553 size_t idx
= HASH_SIZE
;
554 if (insn
->get_mask() % HASH_SIZE
== HASH_SIZE
- 1)
555 idx
= insn
->get_match() % HASH_SIZE
;
556 chain
[idx
].push_back(insn
);
559 disassembler_t::~disassembler_t()
561 for (size_t i
= 0; i
< HASH_SIZE
+1; i
++)
562 for (size_t j
= 0; j
< chain
[i
].size(); j
++)