1 // See LICENSE for license details.
11 struct : public arg_t
{
12 std::string
to_string(insn_t insn
) const {
13 return std::to_string((int)insn
.i_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
17 struct : public arg_t
{
18 std::string
to_string(insn_t insn
) const {
19 return std::to_string((int)insn
.s_imm()) + '(' + xpr_name
[insn
.rs1()] + ')';
23 struct : public arg_t
{
24 std::string
to_string(insn_t insn
) const {
25 return std::string("0(") + xpr_name
[insn
.rs1()] + ')';
29 struct : public arg_t
{
30 std::string
to_string(insn_t insn
) const {
31 return xpr_name
[insn
.rd()];
35 struct : public arg_t
{
36 std::string
to_string(insn_t insn
) const {
37 return xpr_name
[insn
.rs1()];
41 struct : public arg_t
{
42 std::string
to_string(insn_t insn
) const {
43 return xpr_name
[insn
.rs2()];
47 struct : public arg_t
{
48 std::string
to_string(insn_t insn
) const {
49 return fpr_name
[insn
.rd()];
53 struct : public arg_t
{
54 std::string
to_string(insn_t insn
) const {
55 return fpr_name
[insn
.rs1()];
59 struct : public arg_t
{
60 std::string
to_string(insn_t insn
) const {
61 return fpr_name
[insn
.rs2()];
65 struct : public arg_t
{
66 std::string
to_string(insn_t insn
) const {
67 return fpr_name
[insn
.rs3()];
71 struct : public arg_t
{
72 std::string
to_string(insn_t insn
) const {
75 #define DECLARE_CSR(name, num) case num: return #name;
78 default: return "unknown";
83 struct : public arg_t
{
84 std::string
to_string(insn_t insn
) const {
85 return std::to_string((int)insn
.i_imm());
89 struct : public arg_t
{
90 std::string
to_string(insn_t insn
) const {
92 s
<< std::hex
<< "0x" << ((uint32_t)insn
.u_imm() >> 12);
97 struct : public arg_t
{
98 std::string
to_string(insn_t insn
) const {
99 return std::to_string(insn
.rs1());
103 struct : public arg_t
{
104 std::string
to_string(insn_t insn
) const {
106 int32_t target
= insn
.sb_imm();
107 char sign
= target
>= 0 ? '+' : '-';
108 s
<< "pc " << sign
<< ' ' << abs(target
);
113 struct : public arg_t
{
114 std::string
to_string(insn_t insn
) const {
116 int32_t target
= insn
.uj_imm();
117 char sign
= target
>= 0 ? '+' : '-';
118 s
<< "pc " << sign
<< std::hex
<< " 0x" << abs(target
);
123 struct : public arg_t
{
124 std::string
to_string(insn_t insn
) const {
125 return xpr_name
[insn
.rvc_rs1()];
129 struct : public arg_t
{
130 std::string
to_string(insn_t insn
) const {
131 return xpr_name
[insn
.rvc_rs2()];
135 struct : public arg_t
{
136 std::string
to_string(insn_t insn
) const {
137 return xpr_name
[insn
.rvc_rs1s()];
141 struct : public arg_t
{
142 std::string
to_string(insn_t insn
) const {
143 return xpr_name
[insn
.rvc_rs2s()];
147 struct : public arg_t
{
148 std::string
to_string(insn_t insn
) const {
149 return xpr_name
[insn
.rvc_rds()];
153 struct : public arg_t
{
154 std::string
to_string(insn_t insn
) const {
155 return xpr_name
[X_SP
];
159 struct : public arg_t
{
160 std::string
to_string(insn_t insn
) const {
161 return std::to_string((int)insn
.rvc_imm());
165 struct : public arg_t
{
166 std::string
to_string(insn_t insn
) const {
167 return std::to_string((int)insn
.rvc_addi4spn_imm());
171 struct : public arg_t
{
172 std::string
to_string(insn_t insn
) const {
173 return std::to_string((int)insn
.rvc_addi16sp_imm());
177 struct : public arg_t
{
178 std::string
to_string(insn_t insn
) const {
179 return std::to_string((int)insn
.rvc_lwsp_imm());
183 struct : public arg_t
{
184 std::string
to_string(insn_t insn
) const {
185 return std::to_string((int)(insn
.rvc_imm() & 0x3f));
189 struct : public arg_t
{
190 std::string
to_string(insn_t insn
) const {
192 s
<< std::hex
<< "0x" << (uint32_t)insn
.rvc_imm();
197 struct : public arg_t
{
198 std::string
to_string(insn_t insn
) const {
199 return std::to_string((int)insn
.rvc_lwsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
203 struct : public arg_t
{
204 std::string
to_string(insn_t insn
) const {
205 return std::to_string((int)insn
.rvc_ldsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
209 struct : public arg_t
{
210 std::string
to_string(insn_t insn
) const {
211 return std::to_string((int)insn
.rvc_swsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
215 struct : public arg_t
{
216 std::string
to_string(insn_t insn
) const {
217 return std::to_string((int)insn
.rvc_sdsp_imm()) + '(' + xpr_name
[X_SP
] + ')';
221 struct : public arg_t
{
222 std::string
to_string(insn_t insn
) const {
223 return std::to_string((int)insn
.rvc_lw_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
227 struct : public arg_t
{
228 std::string
to_string(insn_t insn
) const {
229 return std::to_string((int)insn
.rvc_ld_imm()) + '(' + xpr_name
[insn
.rvc_rs1s()] + ')';
233 struct : public arg_t
{
234 std::string
to_string(insn_t insn
) const {
236 int32_t target
= insn
.rvc_b_imm();
237 char sign
= target
>= 0 ? '+' : '-';
238 s
<< "pc " << sign
<< ' ' << abs(target
);
243 struct : public arg_t
{
244 std::string
to_string(insn_t insn
) const {
246 int32_t target
= insn
.rvc_j_imm();
247 char sign
= target
>= 0 ? '+' : '-';
248 s
<< "pc " << sign
<< ' ' << abs(target
);
253 std::string
disassembler_t::disassemble(insn_t insn
)
255 const disasm_insn_t
* disasm_insn
= lookup(insn
);
256 return disasm_insn
? disasm_insn
->to_string(insn
) : "unknown";
259 disassembler_t::disassembler_t()
261 const uint32_t mask_rd
= 0x1fUL
<< 7;
262 const uint32_t match_rd_ra
= 1UL << 7;
263 const uint32_t mask_rs1
= 0x1fUL
<< 15;
264 const uint32_t match_rs1_ra
= 1UL << 15;
265 const uint32_t mask_rs2
= 0x1fUL
<< 20;
266 const uint32_t mask_imm
= 0xfffUL
<< 20;
267 const uint32_t match_imm_1
= 1UL << 20;
268 const uint32_t mask_rvc_rs2
= 0x1fUL
<< 2;
269 const uint32_t mask_rvc_imm
= mask_rvc_rs2
| 0x1000UL
;
271 #define DECLARE_INSN(code, match, mask) \
272 const uint32_t match_##code = match; \
273 const uint32_t mask_##code = mask;
274 #include "encoding.h"
277 // explicit per-instruction disassembly
278 #define DISASM_INSN(name, code, extra, ...) \
279 add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
280 #define DEFINE_NOARG(code) \
281 add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
282 #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
283 #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
284 #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
285 #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
286 #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
287 #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
288 #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
289 #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
290 #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
291 #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
292 #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
293 #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
294 #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
295 #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
296 #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
297 #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
298 #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
299 #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
300 #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
315 DEFINE_XAMO(amoadd_w
)
316 DEFINE_XAMO(amoswap_w
)
317 DEFINE_XAMO(amoand_w
)
319 DEFINE_XAMO(amoxor_w
)
320 DEFINE_XAMO(amomin_w
)
321 DEFINE_XAMO(amomax_w
)
322 DEFINE_XAMO(amominu_w
)
323 DEFINE_XAMO(amomaxu_w
)
324 DEFINE_XAMO(amoadd_d
)
325 DEFINE_XAMO(amoswap_d
)
326 DEFINE_XAMO(amoand_d
)
328 DEFINE_XAMO(amoxor_d
)
329 DEFINE_XAMO(amomin_d
)
330 DEFINE_XAMO(amomax_d
)
331 DEFINE_XAMO(amominu_d
)
332 DEFINE_XAMO(amomaxu_d
)
345 add_insn(new disasm_insn_t("j", match_jal
, mask_jal
| mask_rd
, {&jump_target
}));
346 add_insn(new disasm_insn_t("jal", match_jal
| match_rd_ra
, mask_jal
| mask_rd
, {&jump_target
}));
347 add_insn(new disasm_insn_t("jal", match_jal
, mask_jal
, {&xrd
, &jump_target
}));
349 DEFINE_B1TYPE("beqz", beq
);
350 DEFINE_B1TYPE("bnez", bne
);
351 DEFINE_B1TYPE("bltz", blt
);
352 DEFINE_B1TYPE("bgez", bge
);
363 add_insn(new disasm_insn_t("ret", match_jalr
| match_rs1_ra
, mask_jalr
| mask_rd
| mask_rs1
| mask_imm
, {}));
364 DEFINE_I2TYPE("jr", jalr
);
365 add_insn(new disasm_insn_t("jalr", match_jalr
| match_rd_ra
, mask_jalr
| mask_rd
| mask_imm
, {&xrs1
}));
368 add_insn(new disasm_insn_t("nop", match_addi
, mask_addi
| mask_rd
| mask_rs1
| mask_imm
, {}));
369 add_insn(new disasm_insn_t(" - ", match_xor
, mask_xor
| mask_rd
| mask_rs1
| mask_rs2
, {})); // for machine-generated bubbles
370 DEFINE_I0TYPE("li", addi
);
371 DEFINE_I1TYPE("mv", addi
);
375 add_insn(new disasm_insn_t("seqz", match_sltiu
| match_imm_1
, mask_sltiu
| mask_imm
, {&xrd
, &xrs1
}));
377 add_insn(new disasm_insn_t("not", match_xori
| mask_imm
, mask_xori
| mask_imm
, {&xrd
, &xrs1
}));
383 DEFINE_I1TYPE("sext.w", addiw
);
393 add_insn(new disasm_insn_t("snez", match_sltu
, mask_sltu
| mask_rs1
, {&xrd
, &xrs2
}));
403 DEFINE_RTYPE(mulhsu
);
420 DEFINE_NOARG(sbreak
);
422 DEFINE_NOARG(fence_i
);
424 add_insn(new disasm_insn_t("csrr", match_csrrs
, mask_csrrs
| mask_rs1
, {&xrd
, &csr
}));
425 add_insn(new disasm_insn_t("csrw", match_csrrw
, mask_csrrw
| mask_rd
, {&csr
, &xrs1
}));
426 add_insn(new disasm_insn_t("csrs", match_csrrs
, mask_csrrs
| mask_rd
, {&csr
, &xrs1
}));
427 add_insn(new disasm_insn_t("csrc", match_csrrc
, mask_csrrc
| mask_rd
, {&csr
, &xrs1
}));
428 add_insn(new disasm_insn_t("csrwi", match_csrrwi
, mask_csrrwi
| mask_rd
, {&csr
, &zimm5
}));
429 add_insn(new disasm_insn_t("csrsi", match_csrrsi
, mask_csrrsi
| mask_rd
, {&csr
, &zimm5
}));
430 add_insn(new disasm_insn_t("csrci", match_csrrci
, mask_csrrci
| mask_rd
, {&csr
, &zimm5
}));
431 add_insn(new disasm_insn_t("csrrw", match_csrrw
, mask_csrrw
, {&xrd
, &csr
, &xrs1
}));
432 add_insn(new disasm_insn_t("csrrs", match_csrrs
, mask_csrrs
, {&xrd
, &csr
, &xrs1
}));
433 add_insn(new disasm_insn_t("csrrc", match_csrrc
, mask_csrrc
, {&xrd
, &csr
, &xrs1
}));
434 add_insn(new disasm_insn_t("csrrwi", match_csrrwi
, mask_csrrwi
, {&xrd
, &csr
, &zimm5
}));
435 add_insn(new disasm_insn_t("csrrsi", match_csrrsi
, mask_csrrsi
, {&xrd
, &csr
, &zimm5
}));
436 add_insn(new disasm_insn_t("csrrci", match_csrrci
, mask_csrrci
, {&xrd
, &csr
, &zimm5
}));
439 DEFINE_FRTYPE(fadd_s
);
440 DEFINE_FRTYPE(fsub_s
);
441 DEFINE_FRTYPE(fmul_s
);
442 DEFINE_FRTYPE(fdiv_s
);
443 DEFINE_FR1TYPE(fsqrt_s
);
444 DEFINE_FRTYPE(fmin_s
);
445 DEFINE_FRTYPE(fmax_s
);
446 DEFINE_FR3TYPE(fmadd_s
);
447 DEFINE_FR3TYPE(fmsub_s
);
448 DEFINE_FR3TYPE(fnmadd_s
);
449 DEFINE_FR3TYPE(fnmsub_s
);
450 DEFINE_FRTYPE(fsgnj_s
);
451 DEFINE_FRTYPE(fsgnjn_s
);
452 DEFINE_FRTYPE(fsgnjx_s
);
453 DEFINE_FR1TYPE(fcvt_s_d
);
454 DEFINE_XFTYPE(fcvt_s_l
);
455 DEFINE_XFTYPE(fcvt_s_lu
);
456 DEFINE_XFTYPE(fcvt_s_w
);
457 DEFINE_XFTYPE(fcvt_s_wu
);
458 DEFINE_XFTYPE(fcvt_s_wu
);
459 DEFINE_XFTYPE(fmv_s_x
);
460 DEFINE_FXTYPE(fcvt_l_s
);
461 DEFINE_FXTYPE(fcvt_lu_s
);
462 DEFINE_FXTYPE(fcvt_w_s
);
463 DEFINE_FXTYPE(fcvt_wu_s
);
464 DEFINE_FXTYPE(fclass_s
);
465 DEFINE_FXTYPE(fmv_x_s
);
466 DEFINE_FXTYPE(feq_s
);
467 DEFINE_FXTYPE(flt_s
);
468 DEFINE_FXTYPE(fle_s
);
470 DEFINE_FRTYPE(fadd_d
);
471 DEFINE_FRTYPE(fsub_d
);
472 DEFINE_FRTYPE(fmul_d
);
473 DEFINE_FRTYPE(fdiv_d
);
474 DEFINE_FR1TYPE(fsqrt_d
);
475 DEFINE_FRTYPE(fmin_d
);
476 DEFINE_FRTYPE(fmax_d
);
477 DEFINE_FR3TYPE(fmadd_d
);
478 DEFINE_FR3TYPE(fmsub_d
);
479 DEFINE_FR3TYPE(fnmadd_d
);
480 DEFINE_FR3TYPE(fnmsub_d
);
481 DEFINE_FRTYPE(fsgnj_d
);
482 DEFINE_FRTYPE(fsgnjn_d
);
483 DEFINE_FRTYPE(fsgnjx_d
);
484 DEFINE_FR1TYPE(fcvt_d_s
);
485 DEFINE_XFTYPE(fcvt_d_l
);
486 DEFINE_XFTYPE(fcvt_d_lu
);
487 DEFINE_XFTYPE(fcvt_d_w
);
488 DEFINE_XFTYPE(fcvt_d_wu
);
489 DEFINE_XFTYPE(fcvt_d_wu
);
490 DEFINE_XFTYPE(fmv_d_x
);
491 DEFINE_FXTYPE(fcvt_l_d
);
492 DEFINE_FXTYPE(fcvt_lu_d
);
493 DEFINE_FXTYPE(fcvt_w_d
);
494 DEFINE_FXTYPE(fcvt_wu_d
);
495 DEFINE_FXTYPE(fclass_d
);
496 DEFINE_FXTYPE(fmv_x_d
);
497 DEFINE_FXTYPE(feq_d
);
498 DEFINE_FXTYPE(flt_d
);
499 DEFINE_FXTYPE(fle_d
);
501 DISASM_INSN("ebreak", c_add
, mask_rd
| mask_rvc_rs2
, {});
502 add_insn(new disasm_insn_t("ret", match_c_li
| match_rd_ra
, mask_c_li
| mask_rd
| mask_rvc_imm
, {}));
503 DISASM_INSN("jr", c_li
, mask_rvc_imm
, {&rvc_rs1
});
504 DISASM_INSN("jalr", c_lui
, mask_rvc_imm
, {&rvc_rs1
});
505 DISASM_INSN("nop", c_addi
, mask_rd
| mask_rvc_imm
, {});
506 DISASM_INSN("addi", c_addi
, mask_rd
, {&rvc_sp
, &rvc_sp
, &rvc_addi16sp_imm
});
507 DISASM_INSN("addi", c_addi4spn
, 0, {&rvc_rs1s
, &rvc_sp
, &rvc_addi4spn_imm
});
508 DISASM_INSN("li", c_li
, 0, {&xrd
, &rvc_imm
});
509 DISASM_INSN("lui", c_lui
, 0, {&xrd
, &rvc_uimm
});
510 DISASM_INSN("addi", c_addi
, 0, {&xrd
, &xrd
, &rvc_imm
});
511 DISASM_INSN("addiw", c_addiw
, 0, {&xrd
, &xrd
, &rvc_imm
});
512 DISASM_INSN("slli", c_slli
, 0, {&xrd
, &rvc_shamt
});
513 DISASM_INSN("mv", c_mv
, 0, {&xrd
, &rvc_rs1
});
514 DISASM_INSN("add", c_add
, 0, {&xrd
, &xrd
, &rvc_rs1
});
515 DISASM_INSN("addw", c_addw
, 0, {&xrd
, &xrd
, &rvc_rs1
});
516 DISASM_INSN("lw", c_lwsp
, 0, {&xrd
, &rvc_lwsp_address
});
517 DISASM_INSN("ld", c_ldsp
, 0, {&xrd
, &rvc_ldsp_address
});
518 DISASM_INSN("sw", c_swsp
, 0, {&rvc_rs2
, &rvc_swsp_address
});
519 DISASM_INSN("sd", c_sdsp
, 0, {&rvc_rs2
, &rvc_sdsp_address
});
520 DISASM_INSN("lw", c_lw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
521 DISASM_INSN("ld", c_ld
, 0, {&rvc_rs2s
, &rvc_ld_address
});
522 DISASM_INSN("sw", c_sw
, 0, {&rvc_rs2s
, &rvc_lw_address
});
523 DISASM_INSN("sd", c_sd
, 0, {&rvc_rs2s
, &rvc_ld_address
});
524 DISASM_INSN("beqz", c_beqz
, 0, {&rvc_rs1s
, &rvc_branch_target
});
525 DISASM_INSN("bnez", c_bnez
, 0, {&rvc_rs1s
, &rvc_branch_target
});
526 DISASM_INSN("j", c_j
, 0, {&rvc_jump_target
});
528 // provide a default disassembly for all instructions as a fallback
529 #define DECLARE_INSN(code, match, mask) \
530 add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
531 #include "encoding.h"
535 const disasm_insn_t
* disassembler_t::lookup(insn_t insn
)
537 size_t idx
= insn
.bits() % HASH_SIZE
;
538 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
539 if(*chain
[idx
][j
] == insn
)
540 return chain
[idx
][j
];
543 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
544 if(*chain
[idx
][j
] == insn
)
545 return chain
[idx
][j
];
550 void disassembler_t::add_insn(disasm_insn_t
* insn
)
552 size_t idx
= HASH_SIZE
;
553 if (insn
->get_mask() % HASH_SIZE
== HASH_SIZE
- 1)
554 idx
= insn
->get_match() % HASH_SIZE
;
555 chain
[idx
].push_back(insn
);
558 disassembler_t::~disassembler_t()
560 for (size_t i
= 0; i
< HASH_SIZE
+1; i
++)
561 for (size_t j
= 0; j
< chain
[i
].size(); j
++)