1 // See LICENSE for license details.
8 #include <fesvr/option_parser.h>
18 fprintf(stderr
, "usage: spike [host options] <target program> [target options]\n");
19 fprintf(stderr
, "Host Options:\n");
20 fprintf(stderr
, " -p <n> Simulate <n> processors\n");
21 fprintf(stderr
, " -m <n> Provide <n> MB of target memory\n");
22 fprintf(stderr
, " -d Interactive debug mode\n");
23 fprintf(stderr
, " -g Track histogram of PCs\n");
24 fprintf(stderr
, " -h Print this help message\n");
25 fprintf(stderr
, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
26 fprintf(stderr
, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
27 fprintf(stderr
, " --l2=<S>:<W>:<B> B both powers of 2).\n");
28 fprintf(stderr
, " --extension=<name> Specify RoCC Extension\n");
29 fprintf(stderr
, " --extlib=<name> Shared library to load\n");
33 int main(int argc
, char** argv
)
36 bool histogram
= false;
39 std::unique_ptr
<icache_sim_t
> ic
;
40 std::unique_ptr
<dcache_sim_t
> dc
;
41 std::unique_ptr
<cache_sim_t
> l2
;
42 std::function
<extension_t
*()> extension
;
44 option_parser_t parser
;
46 parser
.option('h', 0, 0, [&](const char* s
){help();});
47 parser
.option('d', 0, 0, [&](const char* s
){debug
= true;});
48 parser
.option('g', 0, 0, [&](const char* s
){histogram
= true;});
49 parser
.option('p', 0, 1, [&](const char* s
){nprocs
= atoi(s
);});
50 parser
.option('m', 0, 1, [&](const char* s
){mem_mb
= atoi(s
);});
51 parser
.option(0, "ic", 1, [&](const char* s
){ic
.reset(new icache_sim_t(s
));});
52 parser
.option(0, "dc", 1, [&](const char* s
){dc
.reset(new dcache_sim_t(s
));});
53 parser
.option(0, "l2", 1, [&](const char* s
){l2
.reset(cache_sim_t::construct(s
, "L2$"));});
54 parser
.option(0, "extension", 1, [&](const char* s
){extension
= find_extension(s
);});
55 parser
.option(0, "extlib", 1, [&](const char *s
){
56 void *lib
= dlopen(s
, RTLD_NOW
| RTLD_GLOBAL
);
58 fprintf(stderr
, "Unable to load extlib '%s': %s\n", s
, dlerror());
63 auto argv1
= parser
.parse(argv
);
66 std::vector
<std::string
> htif_args(argv1
, (const char*const*)argv
+ argc
);
67 sim_t
s(nprocs
, mem_mb
, htif_args
);
69 if (ic
&& l2
) ic
->set_miss_handler(&*l2
);
70 if (dc
&& l2
) dc
->set_miss_handler(&*l2
);
71 for (size_t i
= 0; i
< nprocs
; i
++)
73 if (ic
) s
.get_core(i
)->get_mmu()->register_memtracer(&*ic
);
74 if (dc
) s
.get_core(i
)->get_mmu()->register_memtracer(&*dc
);
75 if (extension
) s
.get_core(i
)->register_extension(extension());
79 s
.set_histogram(histogram
);